SLVSHS7 October   2024 TPSI31P1-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristic Curves
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Transmission of the Enable State
      2. 6.3.2 Power Transmission
      3. 6.3.3 Gate Driver
      4. 6.3.4 Chip Enable (CE)
      5. 6.3.5 Comparators
      6. 6.3.6 VDDP, VDDH, and VDDM Under-voltage Lockout (UVLO)
      7. 6.3.7 Keep-off Circuitry
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 CDIV1, CDIV2 Capacitance
      3. 7.2.3 Application Curves
      4. 7.2.4 Insulation Lifetime
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

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発注情報

5.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 1µF, CDIV1 = 47nF, CDIV2 = 220nF,  CVDRV = 1nF. 50kΩ pull-up from PGOOD to VDDP.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER and DRIVER
tLO_EN Low time of EN.  VVDDH = steady state. 5 µs
tHI_EN High time of EN. VVDDH = steady state. 5 µs
tPER_EN Period of EN. VVDDH = steady state. 10 µs
tLH_VDDH Propagation delay time from VDDP rising to VDDH at 50% level. EN = 0V,
VVDDP =  0V → 5V at 1V/µs,
VVDDH = 7.5V.		 145 µs
tLH_VDRV Propagation delay time from EN rising to VDRV at 90% level VVDDP = 5V,
VVDDH steady state,
EN = 0V → 5V,
VVDRV = 13.5V.		 3 4.5 µs
tHL_VDRV Propagation delay time from EN falling to VDRV at 10% level VVDDP = 5V,
VVDDH steady state,
EN = 5V → 0V,
VVDRV = 1.5V.		 2.5 3.0 µs
tHL_VDRV_PD Propagation delay time from VDDP falling to VDRV at 10% level. Timeout mechanism due to loss of power on primary supply. EN = 5V,
VVDDP =  5V → 0V at -1V/µs,
VVDRV = 1.5V.		 140 160 µs
tLH_VDRV_CE Propagation delay time from CE rising to VDRV at 10% level VVDDP = 5V,
VDDH and VDDM fully discharged.
EN = CE = 0V → 5V,
VVDRV = 1.5V.		 185 µs
tHL_VDRV_CE Propagation delay time from CE falling to VDRV at 10% level VVDDP = 5V,
VVDDH steady state,
EN = 5V,
CE= 5V → 0V,
VVDRV = 1.5V.		 3 4 µs
tR_VDRV VDRV rise time from EN rising to VDRV from 15% to 85% level VVDDP = 5V,
VVDDH steady state,
EN =  0V → 5V,
VVDRV = 2.25V to 12.75V.		 10 ns
tF_VDRV VDRV fall time from EN falling to VDRV from 85% to 15% level VVDDP = xV,
VVDDH steady state,
EN = xV → 0V,
VVDRV = 12.75V to 2.25V.		 10 ns
COMPARATORS
tPD_CMP_VDRV Propagation delay time, comparator input to VDRV asserted low or high. EN = CE = VDDP
VUD = 100mV
VOD = 30mV
Measure VIS+ crossing VREF+, VREF- to 50% VVDRV.		 320 395 460 ns