JAJSPL6A October   2023  – December 2023 TPSM365R1 , TPSM365R15

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable, Shutdown, and Start-Up
      2. 7.3.2  External CLK SYNC (With MODE/SYNC)
        1. 7.3.2.1 Pulse Dependent MODE/SYNC Pin Control
      3. 7.3.3  Adjustable Switching Frequency (with RT)
      4. 7.3.4  Power-Good Output Operation
      5. 7.3.5  Internal LDO, VCC UVLO, and VOUT/FB Input
      6. 7.3.6  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      7. 7.3.7  Output Voltage Selection
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Soft Start and Recovery from Dropout
        1. 7.3.9.1 Soft Start
        2. 7.3.9.2 Recovery from Dropout
      10. 7.3.10 Current Limit and Short Circuit
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Input Supply Current
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode - Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode - Light Load Operation
        4. 7.4.3.4 Minimum On-time Operation
        5. 7.4.3.5 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Choosing the Switching Frequency
        3. 8.2.2.3  Setting the Output Voltage
        4. 8.2.2.4  Input Capacitor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  VCC
        7. 8.2.2.7  CFF Selection
        8. 8.2.2.8  External UVLO
        9. 8.2.2.9  Power-Good Signal
        10. 8.2.2.10 Maximum Ambient Temperature
        11. 8.2.2.11 Other Connections
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN_R Minimum operating input voltage (rising) Rising threshold 3.4 3.55 V
VIN_F Minimum operating input voltage (falling) Once operating; Falling threshold 2.45 3.0 V
ISD_13p5 Shutdown quiescent current; measured at VIN pin (2) VEN = 0 V; VIN = 13.5 V 0.55 1.1 µA
ISD_24p0 Shutdown quiescent current; measured at VIN pin (2) VEN = 0 V; VIN = 24 V 1 1.7 µA
IQ_13p5_Fixed Non-switching input current; measured at VIN pin (2) VIN = VEN = 13.5 V; VOUT/FB = 5.25 V, VMODE/SYNC = 0 V; Fixed output 0.25 0.672 1.05 µA
IQ_13p5_Adj Non-switching input current; measured at VIN pin (2) VIN = VEN = 13.5 V; VFB = 1.05 V, VMODE/SYNC = 0 V; Adjustable output 13 17 23 µA
IQ_24p0_Fixed Non-switching input current; measured at VIN pin (2) VIN = VEN = 24 V; VOUT/FB = 5.25 V, VMODE/SYNC = 0 V; Fixed output 0.8 1.2 1.7 µA
IQ_24p0_Adj Non-switching input current; measured at VIN pin (2) VIN = VEN = 24 V; VFB = 1.05 V, VMODE/SYNC = 0 V; Adjustable output 14 18 22
µA
IB_13p5 Current into BIAS pin (not switching) (2) VIN = 13.5 V, VOUT/FB = 5.25 V, VRT = 0 V; Fixed output 12 17 24 µA
IB_24p0 Current into BIAS pin (not switching) (2) VIN = 24 V, VOUT/FB = 5.25 V, VMODE/SYNC = 0 V; Fixed output 12 18 24 µA
ENABLE (EN PIN)
VEN-WAKE Enable wake-up threshold 0.4 V
VEN-VOUT Precision enable high level 1.16 1.263 1.36 V
VEN-HYST Enable threshold hysteresis 0.3 0.35 0.4 V
ILKG-EN Enable input leakage current VEN = 3.3 V 0.7 8 nA
INTERNAL LDO
VCC Internal VCC voltage 3.6 V ≤ VIN ≤ 65 V; Adjustable output 3.1 3.15 3.26 V
ICC Bias regulator current limit 60 120 mA
VCC-UVLO Internal VCC undervoltage lockout VCC rising under voltage threshold 3 3.3 3.65 V
VCC-UVLO-HYST Internal VCC under voltage lock-out hysteresis Hysteresis below VCC-UVLO 0.3 0.8 1.2 V
CURRENT LIMITS
ISC-100mA  Short circuit high side current limit (3) 100 mA version 140 167 200
mA
 
ILS-LIMIT-100mA Low side current limit (3) 100 mA version 99 116 135
mA
IPEAK-MIN-100mA Minimum peak inductor current limit (3) PFM Operation, 100 mA version; Duty Cycle = 0% 30 40 50
mA
IL-NEG-100mA Sink current limit (negative) (3) FPWM mode -200 -175 -150 mA
ISC-150mA Short circuit high side current limit (3) 150 mA version 210 250 298
mA
ILS-LIMIT-150mA Low side current limit (3) 150 mA version 150 175 204
mA
IPEAK-MIN-150mA Minimum Peak Inductor Current (3) PFM Operation, 150 mA version; Duty Cycle = 0% 55 70 85
mA
IL-NEG-150mA Sink current limit (negative) (3) FPWM mode -200 -175 -150 mA
IZC Zero cross current (3) Auto mode 0 2.5 5 mA
MOSFETS
RDSON-HS High-side MOSFET on-resistance Load = 100 mA 2.2 Ω
RDSON-LS Low-side MOSFET on-resistance Load = 100 mA 1 Ω
VBOOT-UVLO BOOT - SW UVLO threshold (4) 2.14 2.3 2.42 V
OSCILLATOR (MODE/SYNC)
VSYNC-HIGH Sync input and mode high level threshold 1.8 V
VSYNC-LOW Sync input and mode low level threshold 0.8 V
VSYNC-HYS Sync input hysteresis 230 300 380 mV
tPULSE_H High duration needed to be recognized as a pulse 100 ns
tPULSE_L Low duration needed to be recognized as a pulse 100 ns
tSYNC Maximum Pulse duration to sync to external CLK 6 9 12 µs
tMODE Time delay at one level needed to indicate FPWM or AUTO mode 18 µs
OSCILLATOR (RT)
fOSC_2p2MHz Internal oscillator frequency RT = GND 2.1 2.2 2.3 MHz
fOSC_1p0MHz Internal oscillator frequency RT = VCC 0.93 1 1.05 MHz
fADJ_400kHz Accuracy of external frequency, 400 kHz RT = 39.2 kΩ 0.34 0.4 0.46 MHz
VOLTAGE FEEDBACK (VOUT/FB PIN)
VOUT Output Voltage Accuracy for fixed VOUT VOUT = 3.3-V, VIN = 3.6 V to 65 V, FPWM  3.24 3.3 3.34 V
VOUT Output Voltage Accuracy for fixed VOUT VOUT = 5-V, VIN = 5.5 V to 65 V, FPWM  4.93 5 5.08 V
VREF Internal reference voltage VIN = 3.6 V to 65 V, FPWM mode 0.985 1 1.01 V
IFB FB input current Adjustable output, FB = 1 V 1 30 nA
SOFT START
tSS Time from first SW pulse to VFB at 90% of VREF VIN ≥ 3.6 V 1.85 2.58 3.2 ms
POWER GOOD
PG-OV PGOOD upper threshold - rising % of FB (Adjustable output) or % of VOUT/FB (Fixed output) 106 107 110 %
PG-UV PGOOD lower threshold - falling % of FB (Adjustable output) or % of VOUT/FB (Fixed output) 93 94 96.5 %
PG-HYS PGOOD hysteresis - rising/falling  % of FB (Adjustable output) or % of VOUT/FB (Fixed output) 0.8 1.2 1.8 %
VPG-VALID Minimum input voltage for proper PG function 0.7 0.9 2 V
RPG-EN5p0 PGOOD pulldown resistance VEN = 5.0 V, 1 mA pull-up current 20 40 70 Ω
RPG-EN0 PGOOD pulldown resistance VEN = 0 V, 1 mA pull-up current 15 24 46 Ω
tRESET_FILTER Glitch filter time constant for PG function 15 25 40 µs
tPGOOD_ACT Delay time to PG high signal 1.7 1.956 2.16 ms
PWM LIMITS (SW)
tON-MIN Minimum switch on-time VIN = 24 V, IOUT = 100 mA 40 57 80 ns
tOFF-MIN Minimum switch off-time 40 58 77 ns
tON-MAX Maximum switch on-time HS timeout in dropout 7.6 9 9.8 µs
(1) MIN and MAX limits are 100% production tested at 25ºC. Limits over the operating temperature range verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
(4) When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turned on to recharge the boot capacitor.