JAJSNY9B September   2022  – February 2023 TPSM365R3 , TPSM365R6

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  System Characteristics
    7. 8.7  Typical Characteristics
    8. 8.8  Typical Characteristics: VIN = 12 V
    9. 8.9  Typical Characteristics: VIN = 24 V
    10. 8.10 Typical Characteristics: VIN = 48 V
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Input Voltage Range
      2. 9.3.2  Output Voltage Selection
      3. 9.3.3  Input Capacitors
      4. 9.3.4  Output Capacitors
      5. 9.3.5  Enable, Start-Up, and Shutdown
      6. 9.3.6  External CLK SYNC (with MODE/SYNC)
        1. 9.3.6.1 Pulse-Dependent MODE/SYNC Pin Control
      7. 9.3.7  Switching Frequency (RT)
      8. 9.3.8  Power-Good Output Operation
      9. 9.3.9  Internal LDO, VCC UVLO, and BIAS Input
      10. 9.3.10 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      11. 9.3.11 Spread Spectrum
      12. 9.3.12 Soft Start and Recovery from Dropout
        1. 9.3.12.1 Recovery from Dropout
      13. 9.3.13 Overcurrent Protection (OCP)
      14. 9.3.14 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Active Mode
        1. 9.4.3.1 CCM Mode
        2. 9.4.3.2 AUTO Mode - Light Load Operation
          1. 9.4.3.2.1 Diode Emulation
          2. 9.4.3.2.2 Frequency Reduction
        3. 9.4.3.3 FPWM Mode - Light Load Operation
        4. 9.4.3.4 Minimum On-time (High Input Voltage) Operation
      4. 9.4.4 Dropout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 600-mA and 300-mA Synchronous Buck Regulator for Industrial Applications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 10.2.1.2.2  Output Voltage Setpoint
          3. 10.2.1.2.3  Switching Frequency Selection
          4. 10.2.1.2.4  Input Capacitor Selection
          5. 10.2.1.2.5  Output Capacitor Selection
          6. 10.2.1.2.6  VCC
          7. 10.2.1.2.7  CFF Selection
          8. 10.2.1.2.8  Power-Good Signal
          9. 10.2.1.2.9  Maximum Ambient Temperature
          10. 10.2.1.2.10 Other Connections
        3. 10.2.1.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Ground and Thermal Considerations
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Development Support
        1. 11.1.3.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1 Overview

The TPSM365R6 or TPSM365R3 is an easy-to-use, synchronous buck, DC-DC power module that operates from a 3-V to 65-V supply voltage. The device is intended for step-down conversions from 5-V, 12-V, 24-V, and 48-V supply rails. With an integrated power controller, inductor, and MOSFETs, the TPSM365R6 or TPSM365R3 delivers up to 600-mA or 300-mA DC load current with high efficiency and ultra-low input quiescent current in a very small solution size. Although designed for simple implementation, this device offers flexibility to optimize its usage according to the target application. Control-loop compensation is not required, reducing design time and external component count.

The TPSM365Rx can operate over a wide range of switching frequencies and duty ratios. If the minimum ON-time or OFF-time cannot support the desired duty ratio, the switching frequency gets reduced automatically, maintaining the output voltage regulation. With the right internal loop compensation the system design time with the TPSM365Rx reduces significantly with minimal external components. In addition, the PGOOD output feature with built-in delayed release allows the elimination of the reset supervisor in many applications.

With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin or an external clock signal, the TPSM365Rx incorporates specific features to improve EMI performance in noise-sensitive applications:

  • An optimized package that incorporates flip chip on lead (FCOL) technology and pinout design enables a shielded switch-node layout that mitigates radiated EMI.
  • Pseudo-Random Spread Spectrum (PRSS) modulation reduces peak emissions.
  • Clock synchronization and FPWM mode enable constant switching frequency across the load current range.
Together, these features eliminate the need for any common-mode choke, shielding, and input filter inductor, greatly reducing the complexities and cost of the EMI/EMC mitigation measures.

The TPSM365Rx module also includes inherent protection features for robust system requirements:

  • An open-drain PGOOD indicator for power-rail sequencing and fault reporting
  • Precision enable input with hysteresis, providing:
    • Programmable line undervoltage lockout (UVLO)
    • Remote ON and OFF capability
  • Internally fixed output-voltage soft start with monotonic start-up into prebiased loads
  • Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits
  • Thermal shutdown with automatic recovery

These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for a simple layout, requiring few external components. See Section 10.4 for a layout example.