JAJSI64C November   2019  – September 2021 TPSM53604

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics (VIN = 5 V)
    7. 6.7 Typical Characteristics (VIN = 12 V)
    8. 6.8 Typical Characteristics (VIN = 24 V)
    9. 6.9 Typical Characteristics (VIN = 36 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Switching Frequency
      3. 7.3.3  Input Capacitors
      4. 7.3.4  Output Capacitors
      5. 7.3.5  Output On/Off Enable (EN)
      6. 7.3.6  Programmable Undervoltage Lockout (UVLO)
      7. 7.3.7  Power Good (PGOOD)
      8. 7.3.8  Light Load Operation
      9. 7.3.9  Voltage Dropout
      10. 7.3.10 Overcurrent Protection (OCP)
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Auto Mode
      3. 7.4.3 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Input Capacitors
        4. 8.2.2.4 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Theta JA versus PCB Area
    4. 10.4 Package Specifications
    5. 10.5 EMI
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Limits apply over TA = –40°C to +105°C, VIN = 12 V, VOUT = 3.3 V, IOUT = IOUT maximum, (unless otherwise noted); CIN1 = 2x10 µF, 50-V, 1206 ceramic; CIN2 = 100 nF, 50-V, 0603 ceramic; COUT = 3x22 µF, 25-V, 1210 ceramic. Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT VOLTAGE (VIN)
VINInput voltage rangeOver IOUT range3.8 (1)36V
VIN turn onVIN increasing, IOUT = 0.2 A3.55V
VIN turn offVIN decreasing, IOUT = 0.2 A3.05V
IQQuiescient currentNon-switching, VFB = 1.2 V24µA
ISHDNShutdown supply currentVEN = 0 V, IOUT = 0 A510µA
INTERNAL LDO (V5V)
V5VInternal LDO output voltage appearing at the V5V pin6 V ≤ VIN ≤ 36 V4.7555.25V
FEEDBACK
VFBFeedback voltage(2)–40°C ≤ TJ ≤ +125°C, IOUT = 0.75 A0.98511.015V
Load regulationTA = +25°C, 0.8 A ≤ IOUT ≤ 4 A0.06%
Line regulationTA = +25°C, IOUT = 0.75 A, Over VIN range0.15%
IFBCurrent into FB pinFB = 1 V0.250nA
CURRENT
IOUTOutput currentTA = 25°C04A
IOUTOver-current threshold5.5A
VHCFB pin voltage required to trip short-circuit hiccup mode0.4V
tHCTime between current-limit hiccup burst94ms
ENABLE (EN PIN)
VEN-LDO-HEN input level required to turn on internal LDORising threshold1V
VEN-LDO-LEN input level required to turn off internal LDOFalling threshold0.3V
VEN-HEN input level required to start switchingRising threshold1.21.231.26V
VEN-HYSHysteresis below VEN-HFalling100mV
ILKG-ENEnable input leakage currentVEN = 3.3 V0.2nA
POWER GOOD (PGOOD PIN)
VPG-HIGH-UPVOUT rising (fault)% of FB voltage107%
VPG-HIGH-DNVOUT falling (good)% of FB voltage105%
VPG-LOW-UPVOUT rising (good)% of FB voltage94%
VPG-LOW-DNVOUT falling (fault)% of FB voltage92%
RPGPower-good flag RDSONVEN = 0 V35Ω
VIN-PGMinimum input voltage for proper PGOOD function50-µA, EN = 0 V2V
VPGPGOOD logic low output50-µA, EN = 0 V, VIN = 2 V0.2V
PERFORMANCE
ηEfficiencyIOUT = 2 A, TA = 25°C91%
SOFT START
tSSInternal soft-start time4ms
SWITCHING FREQUENCY
ƒSWSwitching frequencyIOUT = 2 A, TA = 25°C1.4(3)MHz
(1) The recommended minimum VIN is 3.8 V or (VOUT + 1 V), whichever is greater. See the Section 7.3.9 section for more information.
(2) The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.
(3) The typical switching frequency of this device will change based on operating conditions. See the Section 7.4.2 section for more information.