JAJSLL5 September   2021 TPSM5601R5

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics (VIN = 12 V)
    7. 7.7 Typical Characteristics (VIN = 24 V)
    8. 7.8 Typical Characteristics (VIN = 48 V)
    9. 7.9 Typical Characteristics (VIN = 60 V)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Output Voltage (FB)
      2. 8.3.2 Minimum Input Capacitance
      3. 8.3.3 Minimum Output Capacitance
      4. 8.3.4 Precision Enable (EN), Undervoltage Lockout (UVLO), and Hysteresis (HYS)
      5. 8.3.5 Power Good (PGOOD)
      6. 8.3.6 Spread Spectrum Operation
      7. 8.3.7 Overcurrent Protection (OCP)
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Shutdown Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Output Voltage Setpoint
        3. 9.2.2.3 Input Capacitors
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Power Good Signal
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Theta JA Versus PCB Area
      2. 11.2.2 Package Specifications
      3. 11.2.3 EMI
        1. 11.2.3.1 EMI Plots
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-ACFB018D-41C7-46A1-A583-39B6DF5A7082-low.gif Figure 6-1 15-Pin QFN RDA Package (Top View)
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
10 AGND G Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are measured with respect to this pin. This pin must be connected to PGND at a single point. See Section 11.2 for a recommended layout.
5 DNC — Do not connect. Do not connect this pin to ground, to another pin, or to any other voltage. This pin is connected to the internal bootstrap capacitor. This pin must be soldered to an isolated pad.
2 EN I Enable pin. This pin turns the converter on when pulled high and turns off the converter when pulled low. This pin can be connected directly to VIN. Do not float. This pin can be used to set the input undervoltage lockout with two resistors. See Section 8.3.4.
9 FB I Feedback input. Connect the mid-point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND.
3, 6, 13 NC — Not connected. These pins are not connected to any circuitry within the module. Leaving these pins unconnected to any other signal increases spacing near the high voltage pins (VIN, SW, EN, and DNC). However, if the high voltage spacing is not needed in the application, connecting these pins to the PGND plane can help enhance shielding and thermal performance.
15 PGND G Power ground. This is the return current path for the power stage of the device. Connect this pad to the input supply return, load return, and capacitors associated with the VIN and VOUT pins. See Section 11.2 for a recommended layout.
12 PGOOD O Power-good pin. Open-drain output that asserts low if the feedback voltage is not within the specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required and can be tied to the V5V pin or other DC voltage less than 18 V. If not used, this pin can be left open or connected to PGND.
4 SW O Switch node. Do not place any external component on this pin or connect to any signal.
1, 14 VIN I Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these pins and PGND in close proximity to the device.
7, 8 VOUT O Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external output capacitors between these pins and PGND.
11 V5V O Internal 5-V LDO output. Supplies internal control circuits. Do not connect to external loads. This pin can be used as logic supply for the PGOOD pin.
(1) G = Ground, I = Input, O = Output