JAJSLR7B October 2021 – April 2022 TPSM63606
PRODUCTION DATA
Table 9-3 shows the intended input, output, and performance parameters for this application example. With an IBB topology, the module sees a total current of IIN + |–IOUT|, which is highest at minimum input voltage.
Design Parameter | Value |
---|---|
Input voltage range | 9 V to 24 V |
Input voltage UVLO turn on | 8.9 V |
Output voltage | –12 V |
Full-load current | –2.5 A |
Switching frequency | 2 MHz |
Output voltage regulation | ±1% |
Table 9-4 gives the selected buck module power-stage components with availability from multiple vendors. This design uses an all-ceramic output capacitor implementation.
Ref Des | Qty | Specification | Manufacturer(1) | Part Number |
---|---|---|---|---|
CIN1, CIN2, CIN3 | 3 | 10 µF, 50 V, X7R, 1210, ceramic | Kemet | C1210C106K5RACTU |
TDK | CNA6P1X7R1H106K | |||
COUT1, COUT2 | 2 | 22 µF, 16 V, X7R, 1206, ceramic | Murata | GRM31CZ71C226ME15L |
22 µF, 25 V, X7R, 1210, ceramic | Murata | GRM32ER71E226ME15L | ||
AVX | 12103C226KAT4A | |||
47 µF, 16 V, X6S, 1210, ceramic | Murata | GRM32EC81C476ME15L | ||
U1 | 1 | TPSM63606 36-V, 6-A synchronous buck module | Texas Instruments | TPSM63606RDLR |