同期整流式降圧モジュール・ファミリから派生した TPSM63606 は、パワー MOSFET、シールド付きインダクタ、受動部品を Enhanced HotRod™ QFN パッケージに実装した高集積 36V、6A DC/DC ソリューションです。このモジュールは、VIN および VOUT ピンをパッケージの角に配置し、入力および出力コンデンサの配置を最適化しています。モジュールの下面には大きな 4 つのサーマル・パッドがあるため、単純なレイアウトが可能で、製造時の扱いも容易です。
出力電圧が 1V～16V であるため、TPSM63606 は小さな PCB フットプリントで低 EMI の設計を迅速かつ容易に実装できるよう設計されています。このトータル・ソリューションを使用すると、外付け部品はわずか 4 個で済み、設計プロセスで磁気および補償のための部品選択も不要です。
TPSM63606 モジュールは、スペースが制約される用途での小型化と簡素化をめざして設計されているだけでなく、堅牢性の高い性能を実現するためのさまざまな機能を備えています。その例としては、可変入力電圧 UVLO 用のヒステリシス付き高精度イネーブル、抵抗を使ってプログラム可能なスイッチ・ノードのスルーレートおよび拡散スペクトラム・オプションによる EMI 改善、内蔵 VCC、ブートストラップおよび入力コンデンサによる信頼性向上と高密度化、全負荷電流範囲にわたって一定のスイッチング周波数、シーケンシング、障害保護、出力電圧監視用の PGOOD インジケータがあります。
| 部品番号 | パッケージ(1) | 本体サイズ (公称) |
|---|---|---|
| TPSM63606 | B3QFN (20) | 5.0mm × 5.5mm |
| TPSM63606S |
Changes from Revision A (December 2021) to Revision B (April 2022)
Changes from Revision * (October 2021) to Revision A (December 2021)
| Device | Orderable Part Number | Rated Output Current | Junction Temperature Range | Spread Spectrum | Slew-Rate Control | External Sync |
|---|---|---|---|---|---|---|
| TPSM63602 | TPSM63602RDHR | 2 A | –40°C to 125°C | No | Yes | Yes |
| TPSM63603 | TPSM63603RDHR | 3 A | –40°C to 125°C | No | Yes | Yes |
| TPSM63603S | TPSM63603SRDHR | 3 A | –40°C to 125°C | Yes | Yes | Yes |
| TPSM63603E | TPSM63603EXTRDHR | 3 A | –55°C to 125°C | Yes | Yes | Yes |
| TPSM63604 | TPSM63604RDLR | 4 A | –40°C to 125°C | No | Yes | Yes |
| TPSM63606 | TPSM63606RDLR | 6 A | –40°C to 125°C | No | Yes | Yes |
| TPSM63606S | TPSM63606SRDLR | 6 A | –40°C to 125°C | Yes | Yes | Yes |
| TPSM63606E | TPSM63606EXTRDLR | 6 A | –55°C to 125°C | Yes | Yes | Yes |
| Pin | Type(1) | Description | |
|---|---|---|---|
| Name | NO. | ||
| VIN1, VIN2 | 1, 16 | P | Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these pins and PGND in close proximity to the device. |
| SW | 2 | O | Switch node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on this pin must be kept to a minimum to prevent issues with noise and EMI. |
| CBOOT | 3 | I/O | Bootstrap pin for the internal high-side gate driver. A 100-nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage. CBOOT is brought out to use in conjunction with RBOOT to effectively lower the value of the internal series bootstrap resistance to adjust the switch-node slew rate, if necessary. |
| RBOOT | 4 | I/O | External bootstrap resistor connection. Internal to the device, a 100-Ω bootstrap resistor is connected between RBOOT and CBOOT. RBOOT is brought out to use in conjunction with CBOOT to effectively lower the value of the internal series bootstrap resistance to adjust the switch-node slew rate, if necessary. |
| VLDOIN | 5 | P | Input bias voltage. Input to the internal LDO that supplies the internal control circuits. Connect to an output voltage point to improve efficiency. Connect an optional high-quality 0.1-μF to 1-μF capacitor from this pin to ground for improved noise immunity. If the output voltage is above 12 V, connect this pin to ground. |
| AGND | 6, 11 | G | Analog ground. Zero-voltage reference for internal references and logic. All electrical parameters are measured with respect to this pin. These pins must be connected to PGND. See Section 11.2 for a recommended layout. |
| VCC | 7 | O | Internal LDO output. Used as a supply to the internal control circuits. Do not connect to any external loads. A 1-μF capacitor internally connects from VCC to AGND. |
| VOUT1, VOUT2 | 8, 9 | P | Output voltage. These pins are connected to the internal buck inductor. Connect these pins to the output load and connect external output capacitors between these pins and PGND. |
| FB | 10 | I | Feedback input. Connect the midpoint of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. Do not leave open or connect to ground. |
| RT | 12 | I | Frequency setting pin used to set the switching frequency between 200 kHz and 2.2 MHz by placing an external resistor from RT to AGND. Do not leave open or connect to ground. |
| PG | 13 | O | Open-drain power-good monitor output that asserts low if the FB voltage is not within the specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor to a suitable voltage is required. If not used, PG can be left open or connected to GND. |
| EN/SYNC | 14 | I | Precision enable input pin. High = on, Low = off. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable input voltage UVLO. It also functions as the synchronization input pin. Used to synchronize the device switching frequency to a system clock. Triggers on the rising edge of an external clock. A capacitor can be used to AC couple the synchronization signal to this pin. The module can be turned off by using an open-drain/collector device to connect this pin to AGND. Connect an external resistor divider between this pin, VIN and AGND to create an external UVLO. |
| NC | 15 | — | No connection. Tie to GND or leave open. |
| PGND | 17, 18, 19, 20 | G | Power ground. This is the return current path for the power stage of the device. Connect these pads to the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See Section 11.2 for a recommended layout. |
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Input voltage | VIN1, VIN2 to AGND, PGND | –0.3 | 42 | V |
| RBOOT to SW | –0.3 | 5.5 | V | |
| CBOOT to SW | –0.3 | 5.5 | V | |
| VLDOIN to AGND, PGND | –0.3 | min (VVIN + 0.3, 16) | V | |
| EN/SYNC to AGND, PGND | –0.3 | 42 | V | |
| RT to AGND, PGND | –0.3 | 5.5 | V | |
| FB to AGND, PGND | –0.3 | 16 | V | |
| PG to AGND, PGND | 0 | 20 | V | |
| PGND to AGND | –1 | 2 | V | |
| Output voltage |
VCC to AGND, PGND | –0.3 | 5.5 | V |
| SW to AGND, PGND(2) | –0.3 | 42 | V | |
| VOUT1, VOUT2 to AGND, PGND | –0.3 | 16 | V | |
| Input current | PG | 10 | mA | |
| TJ | Junction temperature | –40 | 150 | °C |
| TA | Ambient temperature | –40 | 125 | °C |
| Tstg | Storage temperature | –55 | 150 | °C |
| Peak reflow case temperature | 250 | °C | ||
| Maximum number of reflows allowed | 3 | |||
| Mechanical vibration | MIL-STD-883D, Method 2007.2, 20 Hz to 2 kHz | 20 | G | |
| Mechanical shock | MIL-STD-883D, Method 2002.3, 1 ms, 1/2 sine, mounted | 500 | G | |