JAJSMY9 April   2022 TPSM63606E

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
    8. 7.8 Typical Characteristics (VIN = 12 V)
    9. 7.9 Typical Characteristics (VIN = 24 V)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Precision Enable and Input Voltage UVLO (EN/SYNC)
      7. 8.3.7  Frequency Synchronization (EN/SYNC)
      8. 8.3.8  Spread Spectrum
      9. 8.3.9  Power Good Monitor (PG)
      10. 8.3.10 Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
      11. 8.3.11 Bias Supply Regulator (VCC, VLDOIN)
      12. 8.3.12 Overcurrent Protection (OCP)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High-Efficiency 6-A Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Inverting Buck-Boost Regulator with Negative Output Voltage
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Output Voltage Setpoint
          2. 9.2.2.2.2 Switching Frequency Selection
          3. 9.2.2.2.3 Input Capacitor Selection
          4. 9.2.2.2.4 Output Capacitor Selection
          5. 9.2.2.2.5 Other Considerations
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Design and Layout
    2. 11.2 Layout Example
      1. 11.2.1 Package Specifications
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
9.2.2.2.3 Input Capacitor Selection

Use two 10-µF, 50-V, X7R-dielectric ceramic capacitors in 1210 case size connected symmetrically from the VIN1 and VIN2 pins to PGND as close as possible to the module. More specifically, these capacitors appear from the drain of the internal high-side MOSFET to the source of the low-side MOSFET, effectively connecting from the positive input voltage to the negative output voltage terminals.

The sum of the input and output voltages, VIN + |–VOUT|, is the effective applied voltage across the capacitors. The total effective capacitance at 25°C and input voltages of 12 V and 24 V (corresponding to applied voltages of 24 V and 36 V) is approximately 12 µF and 8 µF, respectively. Check the capacitance versus voltage derating curve in the capacitor data sheet.

Use an additional 10-µF, 50-V capacitor directly across the input. This capacitor is designated as CIN3 and connects across the VIN+ and VIN– terminals as shown in Figure 9-12.