JAJSOB1A November   2022  – December 2023 TPSM63610

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Adjustable Output Voltage (FB)
      3. 7.3.3  Input Capacitors
      4. 7.3.4  Output Capacitors
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Precision Enable and Input Voltage UVLO (EN)
      7. 7.3.7  Frequency Synchronization (SYNC/MODE)
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Power-Good Monitor (PG)
      10. 7.3.10 Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
      11. 7.3.11 Bias Supply Regulator (VCC, VLDOIN)
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High-Efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Connections
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – Inverting Buck-Boost Regulator with Negative Output Voltage
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 IBB Maximum Output Current
          3. 8.2.2.2.3 Switching Frequency Selection
          4. 8.2.2.2.4 Input Capacitor Selection
          5. 8.2.2.2.5 Output Capacitor Selection
          6. 8.2.2.2.6 Other Considerations
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
8.2.1.2.6 Other Connections

Short RBOOT to CBOOT and connect VLDOIN to the 5-V output for best efficiency. To increase phase margin when using an output capacitance close to the minimum in Table 7-1, a feedforward capacitor, designated as CFF can be placed across the upper feedback resistor. Place the zero created by CFF and RFBT higher than one fifth the switching so that it boosts phase but does not significantly increase the crossover frequency. Because this CFF capacitor can conduct noise from the output of the circuit directly to the FB node of the IC, a 4.99-kΩ resistor, RFF, must be placed in series with CFF. If the ESR zero of the output capacitor is below 200 kHz, do not use CFF.