JAJSPB3 November   2022 TPSM82902

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Mode Selection and Device Configuration (MODE/S-CONF)
      2. 7.3.2 Adjustable VO Operation (External Voltage Divider)
      3. 7.3.3 Setable VO Operation (VSET and Internal Voltage Divider)
      4. 7.3.4 Soft Start/Tracking (SS/TR)
      5. 7.3.5 Smart Enable with Precise Threshold
      6. 7.3.6 Power Good (PG)
      7. 7.3.7 Undervoltage Lockout (UVLO)
      8. 7.3.8 Current Limit And Short Circuit Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Width Modulation (PWM) Operation
      2. 7.4.2 AEE (Automatic Efficiency Enhancement)
      3. 7.4.3 Power Save Mode Operation (Auto PFM/PWM)
      4. 7.4.4 100% Duty-Cycle Operation
      5. 7.4.5 Output Discharge Function
      6. 7.4.6 Starting into a Pre-Biased Load
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application with Adjustable Output Voltage
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Programming the Output Voltage
        3. 8.2.2.3 Capacitor Selection
          1. 8.2.2.3.1 Output Capacitor
          2. 8.2.2.3.2 Input Capacitor
          3. 8.2.2.3.3 Soft-Start Capacitor
        4. 8.2.2.4 Tracking Function
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application with Setable VO Using VSET
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
        1. 8.5.2.1 Thermal Considerations
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.1 Layout Guidelines

A proper layout is critical for the operation of a switched mode power supply, even more at high switching frequencies. Therefore, the PCB layout of the TPSM82902 demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation, bad thermal performance, and noise sensitivity.

  • See Figure 8-61 for the recommended layout of the TPSM82902, which is designed for common external ground connections. TI recommends placing all components as close as possible to the package pins. The input and output capacitors placement specifically, must be closest to the VIN, VOUT, and GND pins of the TPSM82902.
  • Provide low capacitive paths (with respect to all other nodes) for traces with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops which conduct an alternating current must outline an area as small as possible, as this area is proportional to the energy radiated.
  • Sensitive nodes like FB needs to be connected with short wires and not nearby high dv/dt signals. As it carries information about the output voltage, it must be connected as close as possible to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R1 and R2, must be kept close to the module and connect directly to those pins and the system ground plane. The same applies to VSET resistor if VSET is used to scale the output voltage.
  • The package uses the pins for power dissipation. Thermal vias on the VIN, VOUT, and GND pins help to spread the heat through the PCB.
  • In case of the EN, and MODE/S-CONF need to be tied to the input supply voltage at VIN, the connection must be made directly at the input capacitor as indicated in the schematics.
  • The SW/NC pin must not be connected to any other traces. For best practice, this pin must be left floating. If the pin is soldered to PCB copper, the pour needs to be: as small as possible, no inner layer connections, no vias, electrically floating, and limited to the pin area as possible.
  • Refer to Figure 8-61 for an example of component placement, routing and thermal design. The recommended layout is implemented on the EVM and shown in its user's guide.