JAJSPL2 October   2024 TPSM82916

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Smart Config (S-CONF)
      2. 6.3.2  Device Enable (EN/SYNC)
      3. 6.3.3  Device Synchronization (EN/SYNC)
      4. 6.3.4  Spread Spectrum Modulation
      5. 6.3.5  Output Discharge
      6. 6.3.6  Undervoltage Lockout (UVLO)
      7. 6.3.7  Power-Good Output
      8. 6.3.8  Noise Reduction and Soft-Start Capacitor (NR/SS)
      9. 6.3.9  Current Limit and Short-Circuit Protection
      10. 6.3.10 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Fixed Frequency Pulse Width Modulation
      2. 6.4.2 Low Duty Cycle Operation
      3. 6.4.3 High Duty Cycle Operation (100% Duty Cycle)
      4. 6.4.4 Second Stage L-C Filter Compensation (Optional)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 External Component Selection
          1. 7.2.2.2.1 Switching Frequency Selection
          2. 7.2.2.2.2 Output Capacitor Selection
          3. 7.2.2.2.3 Ferrite Bead Selection for Second L-C Filter
          4. 7.2.2.2.4 Input Capacitor Selection
          5. 7.2.2.2.5 Setting the Output Voltage
          6. 7.2.2.2.6 NR/SS Capacitor Selection
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • VCE|16
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

TPSM82916 16-Pin VCE QFN-FCMOD Package (Top View) Figure 4-1 16-Pin VCE QFN-FCMOD Package (Top View)
Figure 4-2 16-Pin VCE QFN-FCMOD Package (Bottom View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1, 13, 15 PGND — Power ground connection
2, 12, 16 VIN I Power supply input voltage pin
3 BOOT (NC) I Supply for the internal high-side MOSFET gate driver. This pin is internally connected to a capacitor. Do not connect anything to this pin.
4 PSNS — Power sense ground, connect directly to GND plane
5 NR/SS O A capacitor connected to this pin sets the soft-start time and low frequency noise level of the device.
6 FB O Feedback pin of the device
7 VOUT O VOUT pin. Connect to the recommend output capacitance.
8 VO I Output voltage sense pin. This pin must be connected directly after the first inductor.
9 PG O Open-drain power-good output. This pin is pulled to GND when VOUT is below the power-good threshold. This pin requires a pullup resistor to output a logic high. This pin can be left open or tied to GND if not used.
10 S-CONF O Smart Configuration pin. This pin configures the operation modes of the device. See Section 6.3.1.
11 EN/SYNC I Enable/Disable pin including threshold-comparator. Connect to logic low to disable the device. Pull high to enable the device. This pin has an internal pulldown resistor of typically 500kΩ when the device is disabled. Apply a clock to this pin to synchronize the device
14 SW (NC) O Switch pin of the power stage. This pin is internally connected to the SW of the converter and the inductor. Make these pads as small as possible under the device, and do not connect anything but a test node to the pad if desired.
(1) I = input, O = output