JAJSOX4A march   2023  – june 2023 TPSM83100

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Rating
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics 
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Enable and Soft Start
      3. 8.3.3 Adjustable Output Voltage
      4. 8.3.4 Mode Selection (PFM/FPWM)
      5. 8.3.5 Output Discharge
      6. 8.3.6 Reverse Current Operation
      7. 8.3.7 Protection Features
        1. 8.3.7.1 Input Overvoltage Protection
        2. 8.3.7.2 Output Overvoltage Protection
        3. 8.3.7.3 Short Circuit Protection
        4. 8.3.7.4 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Capacitor Selection
        2. 9.2.2.2 Input Capacitor Selection
        3. 9.2.2.3 Setting the Output Voltage
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design with WEBENCH Tools
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information
    1.     54

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • SIU|8
サーマルパッド・メカニカル・データ
発注情報

9.4.1 Layout Guidelines

The PCB layout is an important step to maintain the high performance of the TPSM83100 device.

  • Place input and output capacitors as close as possible to the module. Traces need to be kept short. Route wide and direct traces to the input and output capacitors results in low trace resistance and low parasitic inductance.