JAJSP72 August 2024 TPSM83102
PRODUCTION DATA
I2C is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see NXP Semiconductors, UM10204 – I2C-Bus Specification and User Manual ). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA, and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and transmits data on the bus under control of the master device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification:
The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values, depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above VIT+(POR) .
The data transfer protocol for standard and fast modes is exactly the same, therefore, it is referred to as F/S-mode in this document. The device supports 7-bit addressing; 10-bit addressing and general call address are not supported. The device 7-bit address is 6Ah (01101010b).
To make sure that the I2C function in the device is correctly reset, it is recommended that the I2C master initiates a STOP condition on the I2C bus after the initial power up of SDA and SCL pullup voltages.