JAJSRZ2 January   2024 TPSM843320E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Module)
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VIN Pins and VIN UVLO
      2. 6.3.2  Enable and Adjustable UVLO
      3. 6.3.3  Adjusting the Output Voltage
      4. 6.3.4  Switching Frequency Selection
      5. 6.3.5  Switching Frequency Synchronization to an External Clock
        1. 6.3.5.1 Internal PWM Oscillator Frequency
        2. 6.3.5.2 Loss of Synchronization
        3. 6.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 6.3.6  Ramp Amplitude Selection
      7. 6.3.7  Soft Start and Prebiased Output Start-Up
      8. 6.3.8  Mode Pin
      9. 6.3.9  Power Good (PGOOD)
      10. 6.3.10 Current Protection
        1. 6.3.10.1 Positive Inductor Current Protection
        2. 6.3.10.2 Negative Inductor Current Protection
      11. 6.3.11 Output Overvoltage and Undervoltage Protection
      12. 6.3.12 Overtemperature Protection
      13. 6.3.13 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Discontinuous Conduction Mode During Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 1.0V Output, 1MHz Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Switching Frequency
          2. 7.2.1.2.2  Output Inductor Selection
          3. 7.2.1.2.3  Output Capacitor
          4. 7.2.1.2.4  Input Capacitor
          5. 7.2.1.2.5  Adjustable Undervoltage Lockout
          6. 7.2.1.2.6  Output Voltage Resistors Selection
          7. 7.2.1.2.7  Bootstrap Capacitor Selection
          8. 7.2.1.2.8  BP5 Capacitor Selection
          9. 7.2.1.2.9  PGOOD Pullup Resistor
          10. 7.2.1.2.10 Current Limit Selection
          11. 7.2.1.2.11 Soft-Start Time Selection
          12. 7.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 7.2.1.2.13 MODE Pin
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Performance
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.2 Enable and Adjustable UVLO

The EN pin provides on and off control of the device. After the EN pin voltage exceeds the threshold voltage, the device begins the start-up sequence. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low operating current state. The EN pin has an internal pullup current source, Ip, allowing the pin to be floated to enable the device by default. Make that leakage currents of anything connected to the EN pin do not exceed the minimum EN pullup current or the device can not be able to start. If an application requires controlling the EN pin, an open drain or open collector output logic can be interfaced with the pin.

When the EN pin voltage exceeds the threshold voltage and the VIN pin voltage exceeds the VIN UVLO threshold, the device begins the start-up sequence. First, the BP5 LDO is enabled and charges the external BP5 capacitor. After the voltage on the BP5 pin exceeds the UVLO threshold, the device enters a power-on delay. During the power-on delay, the values of the pinstrap resistors on the MODE pin (see Section 6.3.8) and SYNC/FSEL pin (see Section 6.3.4) are determined and the control loop is initialized. The power-on delay is typically 600μs. After the power-on delay, soft start begins.

GUID-20231024-SS0I-3ZKM-32TG-M7S6MDSBHHNJ-low.svg Figure 6-1 Start-Up Sequence

An external resistor divider can be added from VIN to the EN pin for adjustable UVLO and hysteresis as shown in Figure 6-2. The EN pin has a small pullup current, Ip, which sets the default state of the pin to enable when no external components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO function because it increases by Ih after the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 1 and Equation 2. When using the adjustable UVLO function, TI recommends 500mV or greater hysteresis. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN pin to ground to filter any glitches on the input voltage.

GUID-67CC7D07-1653-4523-A1B7-6FEBB19C58EB-low.gifFigure 6-2 Adjustable UVLO Using EN
Equation 1. GUID-EA3E9FC2-E6B9-4789-9C86-6AE0D41624B6-low.gif
Equation 2. GUID-4F87516F-D741-43DF-8103-404746CA53B9-low.gif