JAJSRZ2 January   2024 TPSM843320E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Module)
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VIN Pins and VIN UVLO
      2. 6.3.2  Enable and Adjustable UVLO
      3. 6.3.3  Adjusting the Output Voltage
      4. 6.3.4  Switching Frequency Selection
      5. 6.3.5  Switching Frequency Synchronization to an External Clock
        1. 6.3.5.1 Internal PWM Oscillator Frequency
        2. 6.3.5.2 Loss of Synchronization
        3. 6.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 6.3.6  Ramp Amplitude Selection
      7. 6.3.7  Soft Start and Prebiased Output Start-Up
      8. 6.3.8  Mode Pin
      9. 6.3.9  Power Good (PGOOD)
      10. 6.3.10 Current Protection
        1. 6.3.10.1 Positive Inductor Current Protection
        2. 6.3.10.2 Negative Inductor Current Protection
      11. 6.3.11 Output Overvoltage and Undervoltage Protection
      12. 6.3.12 Overtemperature Protection
      13. 6.3.13 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Discontinuous Conduction Mode During Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 1.0V Output, 1MHz Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Switching Frequency
          2. 7.2.1.2.2  Output Inductor Selection
          3. 7.2.1.2.3  Output Capacitor
          4. 7.2.1.2.4  Input Capacitor
          5. 7.2.1.2.5  Adjustable Undervoltage Lockout
          6. 7.2.1.2.6  Output Voltage Resistors Selection
          7. 7.2.1.2.7  Bootstrap Capacitor Selection
          8. 7.2.1.2.8  BP5 Capacitor Selection
          9. 7.2.1.2.9  PGOOD Pullup Resistor
          10. 7.2.1.2.10 Current Limit Selection
          11. 7.2.1.2.11 Soft-Start Time Selection
          12. 7.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 7.2.1.2.13 MODE Pin
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Performance
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.2.1.2.1 Switching Frequency

The first step is to decide on a switching frequency. The TPSM843320E can operate at five different frequencies from 500kHz to 2.2MHz. The fSW is set by the resistor value from the FSEL pin to ground. Typically, the highest switching frequency possible is desired because this switching frequency produces the smallest design size. A high switching frequency allows for smaller inductors and output capacitors compared to a power supply that switches at a lower frequency. The main tradeoff made with selecting a higher switching frequency is extra switching power loss, which hurts the efficiency of the regulator.

The maximum switching frequency for a given application can be limited by the minimum on-time of the regulator. The maximum fSW can be estimated with Equation 4. Using the minimum on-time of 40 ns and 18V maximum input voltage for this application, the maximum switching frequency is 1390kHz. The selected switching frequency must also consider the tolerance of the switching frequency. A switching frequency of 1000kHz was selected for a good balance of design size and efficiency. To set the frequency to 1000kHz, the selected FSEL resistor is 11.8kΩ per Table 6-1.

Equation 4. GUID-3E0A33AE-41A8-47BE-BD8D-92D0D8065883-low.gif

Figure 7-2 shows the maximum recommended input voltage versus output voltage for each FSEL frequency. This graph uses a minimum on-time of 40ns and includes the 10% tolerance of the switching frequency. A minimum on-time of 40ns is used in this graph to provide margin to the minimum controllable on-time to make sure pulses are not skipped at no load. At light loads, the dead-time between the low-side MOSFET turning off and high-side MOSFET turning on contributes to the minimum SW node pulse-width.

GUID-F3E8FFEB-B6B4-4698-84F3-C22AA728718B-low.svgFigure 7-2 Maximum Input Voltage vs Output Voltage

In high output voltage applications, the minimum off-time must also be considered when selecting the switching frequency. When hitting the minimum off-time limits, the operating duty cycle maxes out and the output voltage begins to drop with the input voltage. Equation 5 calculates the maximum switching frequency to avoid this limit. This equation requires the DC resistance of the inductor, RDCR, selected in the following step. A preliminary estimate of 10mΩ can be used but this must be recalculated based on the specifications of the inductor selected. If operating near the maximum fSW limited by the minimum off-time, the increase in resistance at higher temperature must be considered.

Equation 5. GUID-A647F024-5AE5-4D2C-8645-2946CF295E10-low.gif