JAJSNW8A October 2023 – December 2023 TPSM843820
PRODUCTION DATA
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
FB | 1 | I | Feedback pin for output voltage regulation. Connect this pin to the midpoint of a resistor divider to set the output voltage. |
AGND | 2 | — | Ground return for internal analog circuits |
BP5 | 3 | O | Internal 5-V regulator output. Bypass this pin with a 2.2-μF capacitor to AGND. |
PG | 4 | O | Open-drain power-good indicator |
MODE | 5 | I | A resistor to ground selects the current limit, soft-start rate, and PWM ramp amplitude. |
EN | 6 | I | Enable pin. Float to enable, enable and disable with an external signal, or adjust the input undervoltage lockout with a resistor divider. |
PGND | 7, 8, 9 | — | Ground return for the power stage. This pin is internally connected to the source of the low-side MOSFET. |
VIN | 10 | I | Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 47-nF to 100-nF capacitor from VIN to PGND close to IC is required. |
SW | 11 | DNC | Switch node of the module, used for monitoring only |
BOOT | 12 | DNC | Supply for the internal high-side MOSFET gate driver. This pin is monitoring only because the capacitor to SW pin is integrated |
SYNC/FSEL | 13 | I | Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. |
VOUT | 14 | O | Buck output voltage. Connect output capacitors to this node. |
PAD/PGND | 15 | — | Thermal pad connected to PGND |