JAJSPM0B may   2023  – july 2023 TPSM843A26

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN Pins and VIN UVLO
      2. 7.3.2  Internal Bypassing (BP5)
      3. 7.3.3  Enable and Adjustable UVLO
        1. 7.3.3.1 Internal Sequence of Events During Start-up
      4. 7.3.4  Switching Frequency Selection
      5. 7.3.5  Switching Frequency Synchronization to an External Clock
        1. 7.3.5.1 Internal PWM Oscillator Frequency
        2. 7.3.5.2 Loss of Synchronization
        3. 7.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 7.3.6  Remote Sense Amplifier and Adjusting the Output Voltage
      7. 7.3.7  Loop Compensation Guidelines
        1. 7.3.7.1 Output Filter Inductor Tradeoffs
        2. 7.3.7.2 Ramp Capacitor Selection
        3. 7.3.7.3 Output Capacitor Selection
        4. 7.3.7.4 Design Method for Good Transient Response
      8. 7.3.8  Soft Start and Prebiased Output Start-up
      9. 7.3.9  MSEL Pin
      10. 7.3.10 Power Good (PG)
      11. 7.3.11 Output Overload Protection
        1. 7.3.11.1 Positive Inductor Current Protection
        2. 7.3.11.2 Negative Inductor Current Protection
      12. 7.3.12 Output Overvoltage and Undervoltage Protection
      13. 7.3.13 Overtemperature Protection
      14. 7.3.14 Output Voltage Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Discontinuous Conduction Mode During Soft Start
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 1.0-V Output, 1-MHz Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Input Capacitor
          5. 8.2.1.2.5  Adjustable Undervoltage Lockout
          6. 8.2.1.2.6  Output Voltage Resistors Selection
          7. 8.2.1.2.7  Bootstrap Capacitor Selection
          8. 8.2.1.2.8  BP5 Capacitor Selection
          9. 8.2.1.2.9  PG Pullup Resistor
          10. 8.2.1.2.10 Current Limit Selection
          11. 8.2.1.2.11 Soft-Start Time Selection
          12. 8.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 8.2.1.2.13 MSEL Pin
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Performance
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20230120-SS0I-K8KN-F9QL-12TH59WX7Q35-low.svgFigure 5-1 25-Pin B3QFN-RDG Package (Bottom View)
GUID-20230120-SS0I-M8CF-CTQR-BXXXVHZ2GTQ5-low.svgFigure 5-2 25-Pin B3QFN-RDG Package
(Top View)
Table 5-1 Pin Functions
PinType(1)Description
NameNo.
VOUT1,20OOutput voltage for the converter

FB

2IFeedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the mid-point of a resistor divider to set the output voltage.
GOSNS3I Ground sense return and input to the differential remote sense amplifier.
AGND4G Analog ground return
BP55—Bypass pin for the internal analog control circuitry. This pin is bypassed internally. No external bypassing required. A boot capacitor is integrated inside module.
VIN6,7,14,15,23PInput power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 10-nF to 100-nF capacitor from each VIN to PGND as close as possible is recommended.
PGND8,9,12,13,21,22,24,25GGround return for the power stage. These pins are internally connected to the sources of the low side MOSFETs. 21, 22, 24, 25 act as thermal vias to help dissipate heat from the device to PCB.
SW10OSwitch node of the converter. Leave this pin floating.
BOOT11ISupply for the internal high-side MOSFET gate driver. Leave this pin floating.
EN16IEnable pin. Enable the device by floating the enable pin, or tie enable pin to high, or using external signal, or by using UVLO resistors.
PG17OOpen drain power-good indicator
SYNC/FSEL18IFrequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency.
MSEL19IA resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude settings.
(1) I = input, O = output, P = Supply, G = ground