JAJSPM0B may 2023 – july 2023 TPSM843A26
PRODUCTION DATA
The TPSM843A26 uses input voltage, duty cycle, and low-side FET current information to generate an internal ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP can be selected with a resistor to AGND on the MSEL pin (see Section 7.3.9). The capacitor options are 1 pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop bandwidth. The following figures show how the loop changes with each ramp setting for the schematic in Figure 8-1.
Many applications perform best with a CRAMP value of 4 pF, however, the user must measure the loop gain and phase to determine the optimum CRAMP value for their specific application.
fSW (kHz) | Lookup1 Value | Lookup2 Value |
---|---|---|
500 | 0.372 | 0.297 |
750 | 0.548 | 0.445 |
1000 | 0.719 | 0.594 |
1500 | 1.04 | 0.891 |
2200 | 1.46 | 1.31 |
Figure 7-6 and Figure 7-7 show how the loop changes with each ramp setting for the schematic in Section 8.