JAJSQX8
august 2023
TPSM843A26E
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
VIN Pins and VIN UVLO
7.3.2
Internal Bypassing (BP5)
7.3.3
Enable and Adjustable UVLO
7.3.3.1
Internal Sequence of Events During Start-up
7.3.4
Switching Frequency Selection
7.3.5
Switching Frequency Synchronization to an External Clock
7.3.5.1
Internal PWM Oscillator Frequency
7.3.5.2
Loss of Synchronization
7.3.5.3
Interfacing the SYNC/FSEL Pin
7.3.6
Remote Sense Amplifier and Adjusting the Output Voltage
7.3.7
Loop Compensation Guidelines
7.3.7.1
Output Filter Inductor Tradeoffs
7.3.7.2
Ramp Capacitor Selection
7.3.7.3
Output Capacitor Selection
7.3.7.4
Design Method for Good Transient Response
7.3.8
Soft Start and Prebiased Output Start-up
7.3.9
MSEL Pin
7.3.10
Power Good (PG)
7.3.11
Output Overload Protection
7.3.11.1
Positive Inductor Current Protection
7.3.11.2
Negative Inductor Current Protection
7.3.12
Output Overvoltage and Undervoltage Protection
7.3.13
Overtemperature Protection
7.3.14
Output Voltage Discharge
7.4
Device Functional Modes
7.4.1
Forced Continuous-Conduction Mode
7.4.2
Discontinuous Conduction Mode During Soft Start
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
1.0-V Output, 1-MHz Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Switching Frequency
8.2.1.2.2
Output Inductor Selection
8.2.1.2.3
Output Capacitor
8.2.1.2.4
Input Capacitor
8.2.1.2.5
Adjustable Undervoltage Lockout
8.2.1.2.6
Output Voltage Resistors Selection
8.2.1.2.7
Bootstrap Capacitor Selection
8.2.1.2.8
BP5 Capacitor Selection
8.2.1.2.9
PG Pullup Resistor
8.2.1.2.10
Current Limit Selection
8.2.1.2.11
Soft-Start Time Selection
8.2.1.2.12
Ramp Selection and Control Loop Stability
8.2.1.2.13
MSEL Pin
8.2.1.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
8.4.3
Thermal Performance
9
Device and Documentation Support
9.1
ドキュメントの更新通知を受け取る方法
9.2
サポート・リソース
9.3
Trademarks
9.4
静電気放電に関する注意事項
9.5
用語集
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RDG|25
MPQF603
サーマルパッド・メカニカル・データ
発注情報
jajsqx8_oa
6.6
Typical Characteristics
Figure 6-1
High-Side FET Rds
ON
Figure 6-3
Overcurrent Limit
Figure 6-5
Enable Voltage
Figure 6-7
V
IN
UVLO
Figure 6-9
PG Threshold
Figure 6-11
Enable Pin Current at Different VIN
Figure 6-13
Non-Switching Supply Current
Figure 6-15
VDRV vs Temperature
Figure 6-2
Low-Side FET Rds
ON
Figure 6-4
Negative Overcurrent Limit
Figure 6-6
V
REF
Figure 6-8
V
CC
UVLO
Figure 6-10
PG Leakage Current
Figure 6-12
Soft Start
Figure 6-14
Shutdown Supply Current
Figure 6-16
Switching Frequency vs Temperature