The enable feature of the TPSM843A26E provides two-threshold-level functionality. When the EN pin voltage is less than the internal start-up threshold (approximately 0.8 V), the device is in a low-power shutdown mode. When the EN pin voltage rises to above this threshold, the internal linear regulator (LDO) is enabled and charges the external VDRV capacitor. When VCC is connected to VDRV, and the voltage on the VCC pin exceeds its UVLO threshold (approximately 3.6 V), the TPSM843A26E reads the pin strap configuration as determined by the MSEL pin (see Section 7.3.9) and SYNC/FSEL pin (see Section 7.3.5.3) settings, and then enters a standby state.

The second EN pin threshold becomes active when both the VIN UVLO (approximately 4 V) and VCC UVLO thresholds are exceeded. Thus, when the EN pin reaches above the (nominally 1.2 V) upper threshold, the TPSM843A26E initiates a power-on delay (typically 64 μs) to initialize the control loop circuitry. After the power-on delay, the power stage is enabled and soft start begins.

Figure 7-2 Internal Start-up Sequence

If the enable signal rises very quickly, the delay time from EN rising to the beginning of soft start is a function of the time required to power and initialize the device (start-up of the linear regulator, VCC UVLO exceeded, reading pin strap level, initialize feedback circuitry, and so forth), and can take up to 1 ms (typical).