JAJSEK3B January   2018  – JANUARY 2019 TPSM846C24

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VIN = 12 V)
    8. 6.8 Typical Characteristics (VIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum Capacitance Requirements
      2. 7.3.2  Setting the Compensation Network
      3. 7.3.3  Transient Response
      4. 7.3.4  Setting the Output Voltage
      5. 7.3.5  Differential Remote Sense
      6. 7.3.6  Switching Frequency and Synchronization
        1. 7.3.6.1 Setting the Switching Frequency
        2. 7.3.6.2 Synchronization
          1. 7.3.6.2.1 Stand-Alone Device Synchronization
          2. 7.3.6.2.2 Paralleled Devices Synchronization
      7. 7.3.7  Prebiased Output Start-Up
      8. 7.3.8  Power-Good (PGOOD) Indicator
      9. 7.3.9  Linear Regulators BP3 and BP6
      10. 7.3.10 Parallel Application
      11. 7.3.11 Parallel Operation
      12. 7.3.12 Overtemperature Protection
      13. 7.3.13 Overcurrent Protection
      14. 7.3.14 Output Overvoltage and Undervoltage Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
        2. 8.1.2.2 Setting the Output Voltage
        3. 8.1.2.3 Input and Output Capacitance
        4. 8.1.2.4 Selecting the Compensation Components
        5. 8.1.2.5 Setting the Switching Frequency
        6. 8.1.2.6 Power Good (PGOOD)
        7. 8.1.2.7 ON/OFF Control (EN)
      3. 8.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Package Specifications
    4. 10.4 EMI
    5. 10.5 Mounting and Thermal Profile Recommendation
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over –40°C to 105°C free-air temperature range, VIN = 12 V, VOUT = 1.2 V, IOUT = IOUT(max), ƒSW = 500 kHz, CIN1 = 4 × 22 µF, 25 V, 1210 ceramic; CIN2 = 2 × 330 µF, 25 V, electrolytic bulk; COUT1 = 4 × 47 µF, 6.3 V, 1210 ceramic; COUT2 = 2 × 470 µF, 6.3 V, polymer bulk (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN)
VIN Input voltage Over IOUT range 4.5 15 V
VIN_UVLO VIN undervoltage lock out VIN rising 4.5 V
VIN falling 4
IVIN Input operating current EN = 0 V 7.7 12 mA
OUTPUT VOLTAGE (VOUT)
VOUT VOUT adjustable range(2) Over IOUT range 0.5 2 V
Setpoint voltage tolerance RSET = Not loaded, TJ = 25°C, IOUT = 0 A –1% 1%
RSET = 10 kΩ, 1%, TJ = 25°C, IOUT = 0 A(1) –1.5% 1.5%
Temperature variation 0°C < TJ < 85°C, IOUT = 0 A(2) –0.5% 0.5%
–40°C < TJ < 125°C, IOUT = 0 A(2) –1% 1%
Line regulation 4.5 V < VIN < 15 V, IOUT = 0 A ±0.05%
Load regulation Over IOUT range, using remote sense ±0.2%
Output voltage ripple 20-MHz bandwidth 13 mV
OUTPUT CURRENT
IOUT Output current Natural Convection. See SOA graph for derating over temperature. 0 35 A
Overcurrent threshold 42 A
IOC(acc) Overcurrent accuracy –15% 15%
ISH(acc) Output current share accuracy (IOUT1 – IOUT2) ÷ ITOTAL, IOUT ≥ 20 A per module(2) –15% 15%
(IOUTx – ITOTAL) ÷ 2, IOUT < 20 A per module(2) –3 3 A
SOFT START / STOP
tSStart Internal soft-start time 3 ms
tSStop Internal soft-stop time 3 ms
ENABLE (EN)
VEN Enable threshold voltage Enable high voltage 1.3 V
Enable low voltage 0.8 V
Hysteresis on Enable 170 mV
POWER GOOD (PGOOD) AND OVERVOLTAGE / UNDERVOLTAGE THRESHOLD(3)
PGOOD PGOOD output low voltage VIN = 4 V, VOUT = 0 V, IPGOOD = 5 mA 0.3 V
VIN = 0 V, IPGOOD = 80 µA 0.8
PGOOD thresholds VOUT rising Good 95 %VO
Fault 112 %VO
VOUT falling Good 105 %VO
Fault 88 %VO
PERFORMANCE
Efficiency(1) VIN = 12 V, IOUT = 25 A VOUT = 0.8 V 83%
VOUT = 1.2 V 87%
VOUT = 1.8 V 90%
VIN = 5 V, IOUT = 25 A VOUT = 0.8 V 84%
VOUT = 1.2 V 88%
VOUT = 1.8 V 91%
Transient response(1) 10 A / µs load step from
25% to 75% of IOUT(max),
COUT = 1000 µF,
RC = 1 kΩ, CC = 1 nF		 VOUT over/undershoot 60 mV
Recovery time 60 µs
10 A / µs load step from
25% to 75% of IOUT(max),
COUT = 2000 µF,
RC = 665 Ω, CC = 1.5 nF		 VOUT over/undershoot 40 mV
Recovery time 60 µs
10 A / µs load step from
25% to 75% of IOUT(max),
COUT = 4000 µF,
RC = 499 Ω, CC = 2.2 nF		 VOUT over/undershoot 27 mV
Recovery time 60 µs
INTERNAL LDO (BP6, BP3)(3)
VBP6 BP6 regulator output voltage 7.5V ≤ VIN ≤ 15 V, switching 5.85 6.4 6.95 V
VBP6(DO) Dropout voltage (VVIN – VBP6), VIN = 4.5 V, switching 400 mV
VBP3 BP3 regulator output voltage VIN ≥ 4.5 V 3 3.2 3.4 V
THERMAL SHUTDOWN
TSD Junction thermal shutdown temperature 145 160 °C
THYST Thermal shutdown hysteresis 25 °C
CAPACITANCE
CIN External input capacitance ceramic 88 µF
non-ceramic 660
COUT External output capacitance ceramic(4) 188 µF
non-ceramic(4) 940 4000(5)
ESR (6) 5 mΩ
(1) The stated limit of the set-point tolerance includes the tolernace of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance is affected by the tolerance of the external RSET resistor.
(2) Specified by design.
(3) Functionality Verified. Limits specified at internal IC test.
(4) The minimum required output capacitance consists of 4 × 47-µF ceramic capacitors and 2 × 470-µF, 10-mΩ ESR (5 mΩ equivalent).
(5) The proper frequency compensation network values are determined by the total amount of output capacitance (see Setting the Compensation Network).
(6) The maximum ESR refers to the combined equivalent ESR of all non-ceramic output capacitors. For example, two 10-mΩ ESR capacitors have a combined equivalent ESR of 5 mΩ.