JAJSEK3B January   2018  – JANUARY 2019 TPSM846C24

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VIN = 12 V)
    8. 6.8 Typical Characteristics (VIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum Capacitance Requirements
      2. 7.3.2  Setting the Compensation Network
      3. 7.3.3  Transient Response
      4. 7.3.4  Setting the Output Voltage
      5. 7.3.5  Differential Remote Sense
      6. 7.3.6  Switching Frequency and Synchronization
        1. 7.3.6.1 Setting the Switching Frequency
        2. 7.3.6.2 Synchronization
          1. 7.3.6.2.1 Stand-Alone Device Synchronization
          2. 7.3.6.2.2 Paralleled Devices Synchronization
      7. 7.3.7  Prebiased Output Start-Up
      8. 7.3.8  Power-Good (PGOOD) Indicator
      9. 7.3.9  Linear Regulators BP3 and BP6
      10. 7.3.10 Parallel Application
      11. 7.3.11 Parallel Operation
      12. 7.3.12 Overtemperature Protection
      13. 7.3.13 Overcurrent Protection
      14. 7.3.14 Output Overvoltage and Undervoltage Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
        2. 8.1.2.2 Setting the Output Voltage
        3. 8.1.2.3 Input and Output Capacitance
        4. 8.1.2.4 Selecting the Compensation Components
        5. 8.1.2.5 Setting the Switching Frequency
        6. 8.1.2.6 Power Good (PGOOD)
        7. 8.1.2.7 ON/OFF Control (EN)
      3. 8.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Package Specifications
    4. 10.4 EMI
    5. 10.5 Mounting and Thermal Profile Recommendation
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.11 Parallel Operation

To operate two TPSM846C24 devices in parallel, one of the devices must act as the master and the other act as a slave. To configure one of the devices as the slave device, connect a 1-kΩ resistor between the device FB pin and BP3 pin. Additionally, the SYNC, VSHARE, and ISHARE pins of both devices must be connected as shown in Figure 16. Both devices share the same VSHARE voltage. Essentially, the internal COMP voltage is shared between the two devices by connecting the VSHARE pin of each device together. By connecting the ISHARE pins of each device, the sensed current in each phase is compared, then the error current is added into the internal COMP. The resulting voltage is compared with the PWM ramp to generate the PWM pulse. This current sharing loop maintains the current balance between devices.

In addition to sharing the same internal COMP voltage, the VSHARE pin is also used for fault communication between the loop master and slave devices. The VSHARE pin voltage is pulled low if any device encounters any fault conditions so that the other device sharing VSHARE pin is alerted and stops switching accordingly.

When configured for parallel operation, the SYNC pins of the master and the slave must be supplied with a 50% duty cycle clock signal at the desired switching frequency. The master device locks to the rising edge of the clock; the slave locks to the falling edge. The 50% duty cycle requirement insures the modules operate 180° out of phase to minimize ripple. Both the master And Slave module must have an RRT resistor present whose value sets a switching frequency within ±20% of the SYNC clock frequency.

An optional high-frequency capacitor can be added between the VSHARE pin and ground in noisy systems, but the capacitance must not exceed 10 pF.

If operating conditions result in an on-time pulse width of ≤ 150 ns, jitter may be observed on the master and slave PH pins. The addition of a 10-kΩ resistor in series with the ISHARE connection between the devices helps to reduce, but may not eliminate, the jitter.