JAJSEK3B January   2018  – JANUARY 2019 TPSM846C24

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VIN = 12 V)
    8. 6.8 Typical Characteristics (VIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum Capacitance Requirements
      2. 7.3.2  Setting the Compensation Network
      3. 7.3.3  Transient Response
      4. 7.3.4  Setting the Output Voltage
      5. 7.3.5  Differential Remote Sense
      6. 7.3.6  Switching Frequency and Synchronization
        1. 7.3.6.1 Setting the Switching Frequency
        2. 7.3.6.2 Synchronization
          1. 7.3.6.2.1 Stand-Alone Device Synchronization
          2. 7.3.6.2.2 Paralleled Devices Synchronization
      7. 7.3.7  Prebiased Output Start-Up
      8. 7.3.8  Power-Good (PGOOD) Indicator
      9. 7.3.9  Linear Regulators BP3 and BP6
      10. 7.3.10 Parallel Application
      11. 7.3.11 Parallel Operation
      12. 7.3.12 Overtemperature Protection
      13. 7.3.13 Overcurrent Protection
      14. 7.3.14 Output Overvoltage and Undervoltage Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
        2. 8.1.2.2 Setting the Output Voltage
        3. 8.1.2.3 Input and Output Capacitance
        4. 8.1.2.4 Selecting the Compensation Components
        5. 8.1.2.5 Setting the Switching Frequency
        6. 8.1.2.6 Power Good (PGOOD)
        7. 8.1.2.7 ON/OFF Control (EN)
      3. 8.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Package Specifications
    4. 10.4 EMI
    5. 10.5 Mounting and Thermal Profile Recommendation
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

MOL Package
59-Pin BQFN
Top View
TPSM846C24 AnalogSegerPinout.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 10 G Analog ground for the controller circuitry. This pin is internally connected to PGND.
BP_RTN 51 G Return path for VINBP and BP3. This pin is internally connected to PGND, pad 59.
BP3 47 O Output of the internal 3.3-V regulator. Bypass this pin with a minimum of 2.2-µF to BP_RTN. Can be used as a pullup termination voltage for PGOOD and EN signals.
BP6 49 O Output of the internal 6.5-V regulator that powers the driver stage of the device. Bypass this pin with a minimum of 2.2 µF to BP6_RTN.
BP6_RTN 48 G Power ground return path for BP6 bypass cap.
COMP 9 O Output of the error amplifier.
DIFFO 6 O Output of the remote sense differential amplifier. This provides remote sensing for output voltage reporting and the voltage control loop.
DNC 8, 16, 17, 18,
19, 20, 21, 30, 31		 – Do Not Connect. Do not connect these pins to AGND, PGND to a different DNC pin or to any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
EN 12 I EN pin. To enable, pull this pin up to a voltage less than 5.5 V using a 10-kΩ resistor. Pull this pin to AGND to disable the device.
FB 7 I Feedback pin for the control loop.
ISHARE 2 I Current sharing signal for parallel operation.
NC 1, 15 – Not Connected. These pins are internally isolated from any signal and all other pins. Each pin must be soldered to a pad on the PCB. These pins can be left isolated, or connected to AGND or PGND.
PGND 32, 33, 34, 35
36, 42, 43, 54
56, 57, 58, 59		 G Power ground of the device. This is the return current path for the power stage of the device. Connect these pins to the bypass capacitors associated with VIN and VOUT. Connect pads 56, 57, 58, and 59 to the PCB ground planes using multiple vias for optimal thermal performance. All pins must be connected together externally with a copper plane or pour directly under the device.
PGOOD 52 O Power-good indicator. This pin is an open-drain output, which asserts low during any fault conditions. Requires a pullup resistor.
PH 22, 23, 24, 25
26, 27, 28, 29		 O Phase switch node. Do not connect any external components to these pins or tie them to a pin of a different function.
RT 13 I Frequency-setting resistor. To operate the device at its default switching frequency, make no connection to this pin. To operate at a different switching frequency, connect a resistor from this pin to AGND.
RT_SEL 14 I RT resistor select. To operate the device at its default switching frequency, connect this pin to AGND. To operate at a different switching frequency, let this pin float.
SYNC 11 I/O Frequency synchronization pin. In a stand-alone application or as the Master device in a parallel configuration, the SYNC pin is configured as a SYNC-IN pin and power conversion is synchronized to the rising edge of a 50% duty cycle external clock applied to this pin.
For a slave device in a parallel configuration, power conversion is synchronized to the falling edge of the incoming clock.
VIN 44, 45, 46, 53 I Input switching voltage pins. These pins supply voltage to the power switches of the converter.
VINBP 50 I Input power to the controller circuitry. Bypass this pin with a minimum of 1-µF to BP_RTN. This pin is internally connected to VIN.
VOUT 37, 38, 39,
40, 41, 55		 O Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external bypass capacitors between these pins and PGND.
VS+ 4 I Positive input of the remote sense amplifier. Connect this pin to VOUT at the load for best voltage regulation. Do not let this pin float.
VS– 5 I Negative input of the remote sense amplifier. Connect this pin to ground at the load for best voltage regulation. Do not let this pin float.
VSHARE 3 I/O Voltage sharing signal for parallel operation.