TPSM84A22は使いやすい統合電源ソリューションで、10AのDC/DC同期整流降圧型コンバータのTPS54A20を、パワーMOSFET、シールド付きインダクタ、入力および出力コンデンサ、受動部品とともに、低プロファイルのパッケージに搭載したものです。この総合的な電源ソリューションは、電圧を設定する1つの抵抗だけで動作し、設計においてループ補償や磁性部品の選択が不要になります。
完全に統合された電源ソリューションであるため、標準のアプリケーションは追加の入力または出力コンデンサを必要とせず、出力電圧を設定するための外付けの抵抗1つだけで動作します。高い周波数での動作、非常に高速な過渡応答、正確な電圧レギュレーションにより、TPSM84A22は厳しい規制の仕様を満たすことができます。
PCB占有面積9×15mmで、プリント基板へ簡単にハンダ付けでき、コンパクトで低プロファイルのポイント・オブ・ロード設計が可能です。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
TPSM84A22 | QFM | 9.00mm×15.00mm |
型番 | VOUTの可変範囲 |
---|---|
TPSM84A21 | 0.55V~1.35V |
TPSM84A22 | 1.2V~2.05V |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 16 | — | Zero voltage reference for analog control circuitry. Connect RSET between this pin and VADJ close to the device. Do not connect this pin to PGND; the connection is made internal to the device. |
EN/UVLO | 2 | I | Enable and UVLO adjust pin. When this pin voltage is low, the device is disabled. Use an open drain, open collector, or a suitable logic gate device to control the enable function. A resistor divider between this pin, PGND, and VIN adjusts the UVLO voltage. |
ILIM | 3 | I | Current limit setting pin. Leave this open for the full current limit threshold of 15 A. Connect a 47 kΩ resistor between this pin and PGND to reduce the current limit threshold to 11.25 A. |
PGND | 1, 4, 5, 6, 7, 8, 10, 18, 20 | — | Power ground of the device. Connect these pins to the power ground plane of the PCB. Thermal vias to internal ground planes should be added beneath pin 20. |
PGOOD | 12 | O | Power good indicator. This pin is an open-drain output and will assert low if the output voltage is greater than ±5% from the programmed value or due to thermal shutdown, under-voltage, or EN shutdown. A pull-up resistor is required. VG can be used as a PGOOD pull-up source. |
VS+ | 14 | I | Remote sense connection. This pin must be connected to VOUT at the load or at the device pins. Connect the pin to VOUT at the load for improved regulation. |
SYNC | 11 | I | External clock synchronization pin. An external clock signal can be applied to this pin to synchronize the switching frequency within ±10% of the nominal switching frequency (4 MHz). |
VADJ | 15 | I | Output voltage adjust pin. Connecting a resistor between this pin and AGND sets the output voltage. |
VG | 13 | I | Gate driver supply pin. If this pin is left open, an internal LDO will generate the gate driver supply voltage from the VIN pin. To reduce power consumption and improve efficiency, power this pin with an external 5-V supply. This pin can be used as a PGOOD pull-up source. |
VIN | 17, 19 | I | Input Voltage. These pins supply all of the power to the converter. Connect VIN to a supply voltage between 8 V and 14 V. |
VOUT | 9 | O | Output voltage. Connect any external output capacitors between these pins and PGND. |