JAJSD45B December   2016  – July 2017 TPSM84A22

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Package Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage (VADJ)
      2. 7.3.2  Input and Output Capacitance
      3. 7.3.3  Transient Response
        1. 7.3.3.1 Transient Response Waveforms
      4. 7.3.4  Oscillator Frequency
      5. 7.3.5  External Clock Syncronization
      6. 7.3.6  Soft Start
      7. 7.3.7  Power Good (PGOOD)
      8. 7.3.8  Gate Driver (VG)
      9. 7.3.9  Startup into Pre-biased Outputs
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Output Undervoltage/Overvoltage Protection
      13. 7.3.13 Enable (EN)
      14. 7.3.14 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Input and Output Capacitance
        3. 8.2.2.3 Power Good (PGOOD)
        4. 8.2.2.4 External VG Voltage
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 EMI
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPSM84A22 is a synchronous series capacitor step down DC-DC power module. It is used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 10 A. The following design procedure can be used to select components for the TPSM84A22. Alternately, the WEBENCH® software may be used to generate complete designs. When generating a design, the WEBENCH software utilizes an iterative design procedure and accesses comprehensive databases of components. Please visit www.ti.com/webench for more details.

8.2 Typical Application

The TPSM84A22 includes both input and output capacitors internal to the device, therefore it only requires a voltage setting resistor and possibly a pull-up resistor on the PGOOD pin in most applications. Figure 18 shows a typical TPSM84A22 schematic with only the minimum required components.

TPSM84A22 A22TypAppSch2.gif Figure 18. Typical Application Schematic

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 3 and follow the design procedures below.

Table 3. Design Parameters

DESIGN PARAMETER VALUE
Input Voltage VIN 12 V typical
Output Voltage VOUT 1.2 V
Output Current Rating 10 A
Key care-abouts Transient response, small footprint, high efficiency, PGOOD signal
Transient Response Requirements ±2% voltage deviation, 5 A load step, 5 A/µs slew rate

8.2.2 Detailed Design Procedure

8.2.2.1 Setting the Output Voltage

The output voltage of the TPSM84A22 is externally adjustable using a single resistor (RSET). Select the value of RSET from Table 1 or calculate using Equation 5:

Equation 5. TPSM84A22 equation_1_Rset_cal_SLVSDF8.gif

To set the output voltage to 1.2 V, the calculated value for RSET is 734 Ω. The closest E96 value is 732 Ω.

8.2.2.2 Input and Output Capacitance

The TPSM84A22 requires no external input or output capacitance to operate. Input and output capacitors can be added to improve ripple or transient response. However, in this design example as in many applications, no additional input or output capacitors are required.

8.2.2.3 Power Good (PGOOD)

Applications requiring voltage rail sequencing can benefit from the PGOOD signal present with the TPSM84A22. The PGOOD pin is an open drain output. When the output voltage is typically between 95% and 105% of the set point, the PGOOD pin pull-down is released and the pin floats, requiring an external pull-up resistor for a high signal. A 10-kΩ pull-up resistor is placed between the PGOOD pin and an external 5V rail.

8.2.2.4 External VG Voltage

The VG supply rail is used to power the internal gate drivers and other internal supply rails used by the controller. For best efficiency, supply an external 5 V to the VG pin, thereby overriding the internal 4.8 V regulator. Expect a 2-3% efficiency improvement by driving the VG pin with an external 5 V.

8.2.3 Application Curves

TPSM84A22 startup1_2.gif
VIN = 12V VOUT = 1.2V
Figure 19. Start-up Waveform
TPSM84A22 Trans1_8_5App.gif
VIN = 12V VOUT = 1.2 V Load Step = 5 A
Slew Rate = 5 A/µs
Figure 20. Application Transient Response