JAJSP91B October   2023  – May 2024 TPSM86837 , TPSM86838

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  The Adaptive On-Time Control and PWM Operation
      2. 6.3.2  Mode Selection
        1. 6.3.2.1 FCCM Control and Eco-mode Control
      3. 6.3.3  Soft Start and Prebiased Soft Start
      4. 6.3.4  Enable and Adjusting Undervoltage Lockout
      5. 6.3.5  Output Overcurrent Limit and Undervoltage Protection
      6. 6.3.6  Overvoltage Protection
      7. 6.3.7  UVLO Protection
      8. 6.3.8  Thermal Shutdown
      9. 6.3.9  Output Voltage Discharge
      10. 6.3.10 Power Good
      11. 6.3.11 Large Duty Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Standby Operation
      2. 6.4.2 Light Load Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Resistors Selection
        2. 7.2.2.2 Output Filter Selection
        3. 7.2.2.3 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Application Thermal Considerations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.10 Power Good

The TPSM8683x has a built-in power-good (PG) function to indicate whether the output voltage has reached an appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an open-drain output that requires a pullup resistor (to any voltage below 5.5V). TI recommends a pullup resistor of 100 kΩ to pull the pin up to 5V voltage. The pin can sink 10mA of current and maintain the specified logic low level. After the FB pin voltage is between 90% and 110% of the internal reference voltage (VREF) and after a deglitch time of 64µs, the PG turns to high impedance status. The PG pin is pulled low after a deglitch time of 32µs when FB pin voltage is lower than 85% of the internal reference voltage or greater than 115% of the internal reference voltage, or in events of thermal shutdown, EN shutdown, UVLO conditions. VIN must remain present for the PG pin to stay Low. The PG pin logic are shown in Table 6-2.

Table 6-2 Power-Good Pin Logic Table
Device StatePG Logic Status
High ImpedanceLow
Enable (EN = High)VFB does not trigger VPGTH√
VFB triggers VPGTH√
Shutdown (EN = Low)√
UVLO2V < VIN < VUVLO√
Thermal shutdownTJ > TSD√
Power supply removalVIN < 2V√