JAJSLH7A December 2021 – November 2023 TPSM8D6C24
PRODUCTION DATA
| CMD Address | 44h |
| Write Transaction: | Write Word |
| Read Transaction: | Read Word |
| Format: | ULINEAR16 Absolute per VOUT_MODE |
| Phased: | No |
| NVM Backup: | EEPROM |
| Updates: | On-the-fly |
The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage at the sense or output pins that causes an output voltage fault. The VOUT_UV_FAULT_LIMIT sets an undervoltage threshold relative to the current VOUT_COMMAND. Updates to VOUT_COMMAND do not update VOUT_UV_FAULT_LIMIT when the absolute format is used.
When the undervoltage fault condition is triggered, the TPSM8D6C24 responds according to VOUT_UV_FAULT_RESPONSE.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| VOUT_UVF (High Byte) | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| VOUT_UVF (Low Byte) | |||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 15:0 | VOUT_ UVW | RW | NVM | Sets the undervoltage fault limit. Format is per VOUT_ MODE. |
Hardware Mapping and Supported Values
The hardware for VOUT_UV_FAULT_LIMIT is implemented as a fixed percentage relative to the current output voltage target. Depending on the VOUT_MODE setting, the value written to VOUT_UV_FAULT_LIMIT must be mapped to the hardware percentage.
Programmed values not exactly equal to one of the hardware relative values are rounded down to the next available relative value supported by hardware. The hardware supports values from 60% to 95% of VOUT_COMMAND in 2.5% steps.
Attempts to write (44h) VOUT_UV_FAULT_LIMIT to any value outside those specified as valid are considered invalid orr unsupported data and cause the TPSM8D6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.