Timing and electrical characteristics of the PMBus interface specification can be found in the PMB Power Management Protocol Specification, Part 1, revision 1.3 available at http://pmbus.org. The TPSM8D6C24 device supports the 100-kHz, 400-kHz, and 1-MHz bus timing requirements.

The TPSM8D6C24 uses clock stretching during PMBus communication, but only stretches the clock during specific bits of the transaction.

• The TPSM8D6C24 does not stretch the clock during the address byte of any transaction.
• The TPSM8D6C24 can stretch the clock between bit 0 of the command byte and its ACK response.
• The TPSM8D6C24 stretches the clock after bit 0 of the read address of a read transaction.
• The TPSM8D6C24 stretches the clock between bit 0 of the last byte of data and its ACK response
• The TPSM8D6C24 can stretch the clock between bit 1 and bit zero of every fourth byte of data for blocks with more than four bytes of data.

Communication over the PMBus interface can either support the packet error checking (PEC) scheme or not. If the loop controller supplies clock (CLK) pulses for the PEC byte, PEC is used. If the CLK pulses are not present before a STOP, the PEC is not used. If PEC will always be used, consider enabling Require PEC in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS) to configure the TPSM8D6C24 to reject any write transaction that does not include CLK pulses for a PEC byte.

The device supports a subset of the commands in the PMBus 1.3 Power Management Protocol Specification. See Supported PMBus Commands for more information

The TPSM8D6C24 also supports the SMB_ALERT response protocol. The SMB_ALERT response protocol is a mechanism by which the TPSM8D6C24 can alert the bus controller that it has experienced an alert and has important information for the host. The host should process this event and simultaneously access all target devices on the bus that support the protocol through the alert response address. All target devices that are asserting SMB_ALERT must acknowledge this request with their PMBus address. The host performs a modified receive byte operation to get the address of the target device. At this point, the loop controller can use the PMBus status commands to query the target device that caused the alert. For more information on the SMBus alert response protocol, see the system management bus (SMBus) specification. Persistent faults associated with status registers other than (7Eh) STATUS_CML reasserts SMB_ALERT after responding to the host alert response address.

The TPSM8D6C24 contains nonvolatile memory that is used to store configuration settings and scale factors. The settings programmed into the device are not automatically saved into this nonvolatile memory. The (15h) STORE_USER_ALL command must be used to commit the current PMBus settings to nonvolatile memory as device defaults. The settings that are capable of being stored in nonvolatile memory are noted in their detailed descriptions.

All pin programmable values can be committed to nonvolatile memory. The POR default selection between pin programmable values and nonvolatile memory can be selected by the manufacturer-specific (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE) command.