JAJSLH7A December 2021 – November 2023 TPSM8D6C24
PRODUCTION DATA
| CMD Address | 61h |
| Write Transaction: | Write Word |
| Read Transaction: | Read Word |
| Format: | SLINEAR11 per CAPABILITY |
| Phased: | No |
| NVM Backup: | EEPROM or Pin Detection |
| Updates: | On-the-fly |
The TON_RISE command sets the time, in milliseconds, from when the output starts to rise until the voltage has entered the regulation band, which effectively sets the slew rate of the reference DAC during the soft-start period. Note that the rise time is equal to TON_RISE regardless of the value of the target output voltage or VOUT_SCALE_LOOP.
Due to hardware limitations in the resolution of the reference DAC slew-rate control, longer TON_RISE times with higher VOUT_COMMAND voltages can result in some quantization error in the programmed TON_RISE times with several TON_RISE times producing the same VOUT slope and TON_RISE time even with different TON_RISE settings or different TON_RISE times for the same TON_RISE setting and different VOUT_COMMAND voltages.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| TONR_EXP | TONR_MAN | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| TONR_MAN | |||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 15:11 | TONR_ EXP | RW | 11110b | Linear format two’s complement exponent |
| 10:0 | TONR_ MAN | RW | NVM | Linear format two’s complement mantissa |
Attempts to write (61h) TON_RISE beyond the supported range are considered invalid or unsupported data and cause the TPSM8D6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3. TON_RISE supports the range from 0 ms to 31.75 ms in 0.25-ms steps. Values less than 0.5 ms are supported as 0.5 ms.