SLOU186G August   2006  – May 2017 TRF7960 , TRF7961

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Typical Application
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Power Supplies
      1. 6.2.1 Negative Supply Connections
      2. 6.2.2 Digital I/O Interface
      3. 6.2.3 Supply Regulator Configuration
      4. 6.2.4 Power Modes
      5. 6.2.5 Timing Diagrams
    3. 6.3 Receiver - Analog Section
      1. 6.3.1 Received Signal Strength Indicator (RSSI)
      2. 6.3.2 Receiver - Digital Section
      3. 6.3.3 Transmitter
        1. 6.3.3.1 Transmitter - Analog Section
        2. 6.3.3.2 Transmitter - Digital Section
      4. 6.3.4 Direct Mode
      5. 6.3.5 Register Preset
    4. 6.4 Register Descriptions
      1. 6.4.1 Control Registers - Main Configuration Registers
      2. 6.4.2 Control Registers - Sublevel Configuration Registers
      3. 6.4.3 Status Registers
      4. 6.4.4 FIFO Control Registers
    5. 6.5 Direct Commands From MCU to Reader
      1. 6.5.1  Command Codes
      2. 6.5.2  Reset FIFO
      3. 6.5.3  Transmission With CRC
      4. 6.5.4  Transmission Without CRC
      5. 6.5.5  Delayed Transmission With CRC
      6. 6.5.6  Delayed Transmission Without CRC
      7. 6.5.7  Transmit Next Time Slot
      8. 6.5.8  Receiver Gain Adjust
      9. 6.5.9  Test External RF (RSSI at RX Input With TX Off)
      10. 6.5.10 Test Internal RF (RSSI at RX Input With TX On)
      11. 6.5.11 Block Receiver
      12. 6.5.12 Enable Receiver
    6. 6.6 Reader Communication Interface
      1. 6.6.1 Introduction
    7. 6.7 Parallel Interface Communication
      1. 6.7.1 Receive
      2. 6.7.2 Transmit
    8. 6.8 Serial Interface Communication
      1. 6.8.1 SPI Without SS* (Slave Select) Pin
      2. 6.8.2 SPI With SS* (Slave Select) Pin
        1. 6.8.2.1 FIFO Operation
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Schematics
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Supply voltage 6 V
IO Output current 150 mA
TJ Maximum junction temperature Any condition 140 °C
Continuous operation, long-term reliability(2) 125
Tstg Storage temperature range –55 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability or lifetime of the device.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
Machine model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VIN Supply voltage 2.7 5 5.5 V
TJ Operating virtual junction temperature –40 125 °C
TA Operating ambient temperature –40 25 110 °C

5.4 Electrical Characteristics

TYP values at 25°C, MIN and MAX values over operating ambient temperature range, VS = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IPD Supply current in power-down mode All systems disabled, including supply voltage regulators 1 10 µA
IPD2 Supply current in power-down mode 2 The reference voltage generator and VDD_X remain active to support external circuitry. 120 300 µA
ISTBY Supply current in standby mode Oscillator running, supply voltage regulators in low-consumption mode 1.5 4 mA
ION1 Supply current without antenna driver current Oscillator, regulators, RX, and AGC are active, TX is off 10 16 mA
ION2 Supply current with antenna driver current Oscillator, regulators, RX, AGC, and TX are active, Pout = 100 mW 70 mA
ION3 Supply current with antenna driver current Oscillator, regulators, RX, AGC, and TX are all active, Pout = 200 mW 120 mA
BG Band-gap voltage Internal analog reference voltage 1.4 1.6 1.7 V
VPOR Power-on-reset (POR) voltage 1.4 2 2.5 V
VDD_A Regulated supply for analog circuitry 3.1 3.5 3.8 V
VDD_RF Regulated supply for RF circuitry Regulator set for 5-V system with 250-mV difference 4 4.6 5.2 V
VDD_X Regulated supply for external circuitry 3.1 3.4 3.8 V
PPSRR Rejection of external supply noise on the supply VDD_RF regulator The difference between the external supply and the regulated voltage is higher than 250 mV, measured at 212 kHz 20 26 dB
RRFOUT PA driver output resistance Half-power mode 8 12 Ω
Full-power mode 4 6
RRFIN RX_IN1 and RX_IN2 input resistance 5 10 20 kΩ
VRFIN Maximum input voltage At RX_IN1 and RX_IN2 inputs 3.5 VPP
VSENS Input sensitivity fSUBCARRIER = 424 kHz 1.2 2.5 mVPP
fSUBCARRIER = 848 kHz 1.2 3
tSET_PD Setup time after power down 10 20 ms
tSET_STBY Setup time after standby mode 30 100 µs
tREC Recovery time after modulation (ISO/IEC 14443) Modulation signal: sine, 424 kHz, 10 mVpp 60 µs
fSYS_CLK SYS_CLK frequency In PD2 mode EN = 0 and EN2 = 1 30 60 120 kHz
fD_CLKmax Maximum DATA_CLK frequency Depends on capacitive load on the I/O lines, TI recommends 2 MHz(1) 2 4 8 MHz
CLKMAX Maximum CLK frequency 2 MHz
VIL Input logic low 0.2 × VDD_I/O 0.2 × VDD_I/O V
VIH Input logic high 0.8 × VDD_I/O V
ROUT Output resistance of I/O_0 to I/O_7 low_io = H for VDD_I/O < 2.7 V 400 800 Ω
RSYS_CLK Output resistance of SYS_CLK low_io = H for VDD_I/O < 2.7 V 200 400 Ω
(1) Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. The MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load is used).

5.5 Thermal Resistance Characteristics

PACKAGE RθJC
(°C/W)		 RθJA (1)
(°C/W)		 POWER RATING(2)
TA ≤ 25°C TA = 85°C
RHB (32) 31 36.4 2.7 W 1.1 W
(1) This data was taken using the JEDEC standard high-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the temperature at which distortion starts to increase substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability.