SLOS757G December 2011 – March 2020 TRF7962A
PRODUCTION DATA.
In parallel mode, the start condition is generated on the rising edge of the I/O_7 pin while the CLK is high.
This is used to reset the interface logic. Figure 6-11, Figure 6-12, and Figure 6-13 show the sequence of the data, with an 8-bit address word first, followed by data.
Communication is ended by: