SLOS758G December   2011  – March 2020 TRF7963A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Functional Block Diagram
    2. 6.2  Power Supplies
    3. 6.3  Supply Arrangements
    4. 6.4  Supply Regulator Settings
    5. 6.5  Power Modes
    6. 6.6  Receiver – Analog Section
      1. 6.6.1 Main and Auxiliary Receiver
      2. 6.6.2 Receiver Gain and Filter Stages
    7. 6.7  Receiver – Digital Section
      1. 6.7.1 Received Signal Strength Indicator (RSSI)
        1. 6.7.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.7.1.2 External RSSI
    8. 6.8  Oscillator Section
    9. 6.9  Transmitter - Analog Section
    10. 6.10 Transmitter - Digital Section
    11. 6.11 Transmitter – External Power Amplifier or Subcarrier Detector
    12. 6.12 Communication Interface
      1. 6.12.1 General Introduction
      2. 6.12.2 FIFO Operation
      3. 6.12.3 Parallel Interface Mode
      4. 6.12.4 Reception of Air Interface Data
      5. 6.12.5 Data Transmission to MCU
      6. 6.12.6 Serial Interface Communication (SPI)
        1. 6.12.6.1 Serial Interface Mode Without Slave Select (SS)
        2. 6.12.6.2 Serial Interface Mode With Slave Select (SS)
      7. 6.12.7 Direct Mode
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1 Command Codes
      2. 6.13.2 Reset FIFO (0x0F)
      3. 6.13.3 Transmission With CRC (0x11)
      4. 6.13.4 Transmission Without CRC (0x10)
      5. 6.13.5 Block Receiver (0x16)
      6. 6.13.6 Enable Receiver (0x17)
      7. 6.13.7 Test Internal RF (RSSI at RX Input With TX On) (0x18)
      8. 6.13.8 Test External RF (RSSI at RX Input With TX Off) (0x19)
      9. 6.13.9 Register Preset
    14. 6.14 Register Description
      1. 6.14.1 Register Overview
        1. 6.14.1.1 Main Configuration Registers
          1. 6.14.1.1.1 Chip Status Control Register (0x00)
          2. 6.14.1.1.2 ISO Control Register (0x01)
        2. 6.14.1.2 Protocol Subsetting Registers
          1. 6.14.1.2.1 ISO14443B TX Options Register (0x02)
          2. 6.14.1.2.2 ISO14443A High-Bit-Rate and Parity Options Register (0x03)
          3. 6.14.1.2.3 TX Pulse Length Control Register (0x06)
          4. 6.14.1.2.4 RX No Response Wait Time Register (0x07)
          5. 6.14.1.2.5 RX Wait Time Register (0x08)
          6. 6.14.1.2.6 Modulator and SYS_CLK Control Register (0x09)
          7. 6.14.1.2.7 RX Special Setting Register (0x0A)
          8. 6.14.1.2.8 Regulator and I/O Control Register (0x0B)
        3. 6.14.1.3 Status Registers
          1. 6.14.1.3.1 IRQ Status Register (0x0C)
          2. 6.14.1.3.2 Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
          3. 6.14.1.3.3 RSSI Levels and Oscillator Status Register (0x0F)
        4. 6.14.1.4 Test Registers
          1. 6.14.1.4.1 Test Register (0x1A)
          2. 6.14.1.4.2 Test Register (0x1B)
        5. 6.14.1.5 FIFO Control Registers
          1. 6.14.1.5.1 FIFO Status Register (0x1C)
          2. 6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7963A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 System Design
      1. 7.2.1 Layout Considerations
      2. 7.2.2 Impedance Matching TX_Out (Pin 5) to 50 Ω
      3. 7.2.3 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.12.1 General Introduction

The communication interface to the reader can be configured in two ways: with a eight line parallel interface (D0:D7) plus DATA_CLK, or with a 3- or 4-wire Serial Peripheral Interface (SPI). The SPI interface uses traditional master out/slave in (MOSI), master in/slave out (MISO), IRQ, and DATA_CLK lines. The SPI can be operated with or without using the slave select line.

These communication modes are mutually exclusive, which means that only one mode can be used at a time in the application.

When the SPI interface is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be hard-wired according to Table 6-6. At power up, the TRF7963A IC samples the status of these three pins and then enters one of the possible SPI modes in Table 6-6.

samples the status of these three pins. If they are not the same (all high or all low), the IC enters one of the possible SPI modes.

The TRF7963A always behaves as the slave, while the microcontroller (MCU) behaves as the master device. The MCU initiates all communications with the TRF7963A. The TRF7963A makes use of the Interrupt Request (IRQ) pin in both parallel and SPI modes to prompt the MCU for servicing attention.

Table 6-6 Pin Assignment in Parallel and Serial Interface Connection or Direct Mode

PIN PARALLEL PARALLEL DIRECT SPI WITH SS SPI WITHOUT SS
DATA_CLK DATA_CLK DATA_CLK DATA_CLK from master DATA_CLK from master
I/O_7 A/D[7] MOSI(1) = data in (reader in) MOSI(1) = data in (reader in)
I/O_6 A/D[6] Direct mode, data out
(subcarrier or bit stream)		 MISO(2) = data out (MCU out) MISO(2) = data out (MCU out)
I/O_5 (3) A/D[5] Direct mode, strobe (bit clock out) See (3) See (3)
I/O_4 A/D[4] SS (slave select)(4) –
I/O_3 A/D[3] – – –
I/O_2 A/D[2] – At VDD At VDD
I/O_1 A/D[1] – At VDD At VSS
I/O_0 A/D[0] – At VSS At VSS
IRQ IRQ interrupt IRQ interrupt IRQ interrupt IRQ interrupt
(1) MOSI = Master out, slave in
(2) MISO = Master in, slave out
(3) The I/O_5 pin is used only for information when data is put out of the chip (for example, reading 1 byte from the chip). It is necessary first to write in the address of the register (8 clocks) and then to generate another 8 clocks for reading out the data. The I/O_5 pin goes high during the second 8 clocks. But for normal SPI operations I/O_5 pin is not used.
(4) The slave select pin is active low.

Communication is initialized by a start condition, which is expected to be followed by an Address/Command word (Adr/Cmd). The Adr/Cmd word is 8 bits long, and Table 6-7 describes its format.

Table 6-7 Address/Command Word Bit Distribution

BIT DESCRIPTION BIT FUNCTION ADDRESS COMMAND
B7 Command control bit 0 = Address
1 = Command		 0 1
B6 Read/Write 1 = Read
0 = Write		 R/W 0
B5 Continuous address mode 1 = Continuous mode R/W 0
B4 Address/command bit 4 Adr 4 Cmd 4
B3 Address/command bit 3 Adr 3 Cmd 3
B2 Address/command bit 2 Adr 2 Cmd 2
B1 Address/command bit 1 Adr 1 Cmd 1
B0 Address/command bit 0 Adr 0 Cmd 0

The MSB (bit 7) determines if the word is to be used as a command or as an address. The last two columns of Table 6-7 list the function of the separate bits if either address or command is written. Data is expected once the address word is sent. In continuous address mode (continuous mode = 1), the first data that follows the address is written (or read) to (from) the given address. For each additional data, the address is incremented by one. Continuous mode can be used to write to a block of control registers in a single stream without changing the address; for example, setup of the predefined standard control registers from the MCU nonvolatile memory to the reader. In noncontinuous address mode (simple addressed mode), only one data word is expected after the address.

Address Mode is used to write or read the configuration registers or the FIFO. When writing more than 12 bytes to the FIFO, the Continuous Address Mode should be set to 1.

The Command Mode is used to enter a command that results in reader action (for example, initialize transmission, enable reader, and turn reader on or off).

The following examples show the expected communications between an MCU and the TRF7963A.

Table 6-8 lists the format of a continuous address register read, and Figure 6-5 and Figure 6-6 show examples.

Table 6-8 Continuous Address Mode

Start Adr x Data(x) Data(x+1) Data(x+2) Data(x+3) Data(x+4) ... Data(x+n) StopCont
TRF7963A cont_addr_register_write_slos732.pngFigure 6-5 Continuous Address Register Write Example Starting With Register 0x00 (Using SPI With SS Mode)
TRF7963A cont_addr_register_read_slos732.pngFigure 6-6 Continuous Address Register Read Example Starting With Register 0x00 (Using SPI With SS Mode)

Table 6-9 lists the format of a single address register read, and Figure 6-7 and Figure 6-8 show examples.

Table 6-9 Noncontinuous Address Mode (Single Address Mode)

Start Adr x Data(x) Adr y Data(y) ... Adr z Data(z) StopSgl
TRF7963A single_addr_register_write_slos732.pngFigure 6-7 Single Address Register Write Example of Register 0x00 (Using SPI With SS Mode)
TRF7963A single_addr_register_read_slos732.pngFigure 6-8 Single Address Register Read Example of Register 0x00 (Using SPI With SS Mode)

Table 6-10 lists the format of the direct command mode, and Figure 6-9 shows an example.

Table 6-10 Direct Command Mode

Start Cmd x (Optional data or command) Stop
TRF7963A direct_command_example_slos732.pngFigure 6-9 Direct Command Example of Sending 0x0F (Reset) (Using SPI With SS Mode)

The other Direct Command Codes from MCU to TRF7963A are described in Section 6.13.