JAJST54F July   2007  – February 2024 TRS202E

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics: Driver
    7. 5.7  Electrical Characteristics: Receiver
    8. 5.8  Switching Characteristics: Driver
    9. 5.9  Switching Characteristics: Receiver
    10. 5.10 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power
      2. 6.3.2 RS-232 Driver
      3. 6.3.3 RS-232 Receiver
    4. 6.4 Device Functional Modes
      1. 6.4.1 VCC Powered by 5V
      2. 6.4.2 VCC Unpowered
      3. 6.4.3 Truth Tables
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.8 Switching Characteristics: Driver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted; see Figure 7-1)(1)
PARAMETERTEST CONDITIONSMINTYP(2)MAXUNIT
Maximum data rateCL = 50 to 1000pF, one DOUT switching, and RL = 3kΩ to 7kΩ (see Figure 6-1)120kbit/s
tPLH(D)Propagation delay time, low- to high-level outputCL = 2500pF, all drivers loaded, and RL = 3kΩ (see Figure 6-1)2µs
tPHL(D)Propagation delay time, high- to low-level outputCL = 2500pF, all drivers loaded, and RL = 3kΩ (see Figure 6-1)2µs
tsk(p)Pulse skew(3)CL = 150 to 2500pF and RL = 3kΩ to 7kΩ (see Figure 6-2)300ns
SR(tr)Slew rate, transition regionCL = 50 to 1000pF, VCC = 5V, and RL = 3kΩ to 7kΩ (see Figure 6-1)3630V/µs
(1) Test conditions are C1 to C4 = 0.1µF at VCC = 5V + 0.5V.
(2) All typical values are at VCC = 5V and TA = 25°C.
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.