JAJSP97E April 2007 – December 2022 TRS3243E
PRODUCTION DATA
The HBM of ESD testing is shown in Figure 9-2, while Figure 9-3 shows the current waveform that is generated during a discharge into a low impedance. The model consists of a 100-pF capacitor, charged to the ESD voltage of concern, and subsequently discharged into the DUT through a 1.5-kΩ resistor.