JAJSP97E April   2007  – December 2022 TRS3243E

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Detailed Design Procedure
        1. 9.1.1.1 ESD Protection
        2. 9.1.1.2 ESD Test Conditions
        3. 9.1.1.3 Human-Body Model (HBM)
        4. 9.1.1.4 IEC61000-4-2 (Formerly Known as IEC1000-4-2)
  10. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 商標
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Switching Characteristics

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 9-1) (2)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
DRIVER SECTION
Maximum data rateCL = 1000 pF,
One DOUT switching,		RL = 3 kΩ
See Figure 1		250500kbit/s
tsk(p)Pulse skew(3)CL = 150 pF to 2500 pF,RL = 3 kΩ to 7 kΩ, See Figure 2100ns
SR(tr)Slew rate, transition region
(see Figure 1)		VCC = 3.3 V,
RL = 3 kΩ to 7 kΩ,
PRR = 250 kbit/s		CL = 150 pF to 1000 pF630V/μs
CL = 150 pF to 2500 pF430
RECEIVER SECTION
tPLHPropagation delay time, low- to high-level outputCL = 150 pF, See Figure 7-2150ns
tPHLPropagation delay time, high- to low-level output150ns
tenOutput enable timeCL = 150 pF, RL = 3 kΩ, See Figure 7-3200ns
tdisOutput disable time200ns
tsk(p)Pulse skew(3)See Figure 7-250ns
AUTO-POWERDOWN SECTION
tvalidPropagation delay time, low- to high-level outputVCC = 5 V1μs
tinvalidPropagation delay time, high- to low-level outputVCC = 5 V30μs
tenSupply enable timeVCC = 5 V100μs
(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(2) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V + 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.