JAJSG58G January   2005  – January 2019 TS3A5017

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics for 3.3-V Supply
    6. 6.6 Electrical Characteristics for 2.5-V Supply
    7. 6.7 Switching Characteristics for 3.3-V supply
    8. 6.8 Switching Characteristics for 2.5-V supply
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • DBQ|16
  • RGY|16
  • D|16
  • DGV|16
  • RSV|16
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics for 2.5-V Supply

V+ = 2.3 V to 2.7 V, TA = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS TA V+ MIN TYP MAX UNIT
Analog Switch
VD, VS Analog signal
range		 0 V+ V
ron ON-state
resistance		 0 ≤ VS ≤ V+,
ID = –24 mA,		 Switch ON,
see Figure 12 		25°C 2.3 V 20.5 22 Ω
Full 24
Δron ON-state
resistance match between channels		 VS = 1.6 V,
ID = –24 mA,		 Switch ON,
see Figure 12 		25°C 2.3 V 1 2 Ω
Full 3
ron(flat) ON-state
resistance flatness		 0 ≤ VS ≤ V+,
ID = –24 mA,		 Switch ON,
see Figure 12 		25°C 2.3 V 16 18 Ω
Full 20
IS(OFF) S
OFF leakage
current		 VS = 0.5 V, VD = 2.2 V,
or
VS = 2.2 V, VD = 0.5 V,		 Switch OFF,
see Figure 13 		25°C 2.7 V –0.1 0.05 0.1 μA
Full –0.2 0.2
ISPWR(OFF) VS = 0 to 2.7 V,
VD = 2.7 V to 0,		 25°C 0 V –1 0.5 1
Full –5 5
ID(OFF) D
OFF leakage
current		 VS = 0.5 V, VD = 2.2 V,
or
VS = 2.2 V, VD = 0.5V,		 Switch OFF,
see Figure 13 		25°C 2.7 V –0.1 0.05 0.1 μA
Full –0.2 0.2
IDPWR(OFF) VD = 0 to 2.7 V,
VS = 2.7 V to 0,		 25°C 0 V –1 0.5 1
Full –5 5
IS(ON) S
ON leakage
current		 VS = 0.5 V, VD = Open,
or
VS = 2.2 V, VD = Open,		 Switch ON,
see Figure 14 		25°C 2.7 V –0.1 0.05 0.1 μA
Full –0.2 0.2
ID(ON) D
ON leakage
current		 VD = 0.5 V, VS = Open,
or
VD = 2.2 V, VS = Open,		 Switch ON,
see Figure 14 		25°C 2.7 V –0.1 0.05 0.1 μA
Full –0.2 0.2
Digital Control Inputs (IN1, IN2, EN)(2)
VIH Input logic high Full 1.7 V+ V
VIL Input logic low Full 0 0.7 V
IIH, IIL Input leakage
current		 VI = V+ or 0 25°C 2.7 V –1 0.05 1 μA
Full –1 1
QC Charge injection VGEN = 0, RGEN = 0,
CL = 0.1 nF,		 See Figure 21 25°C 2.5 V pC
CS(OFF) S
OFF capacitance		 VS = V+ or GND,
Switch OFF,		 See Figure 15 25°C 2.5 V 4.5 pF
CD(OFF) D
OFF capacitance		 VD = V+ or GND,
Switch OFF,		 See Figure 15 25°C 2.5 V 18.5 pF
CS(ON) S
ON capacitance		 VS = V+ or GND,
Switch ON,		 See Figure 15 25°C 2.5 V 24 pF
CD(ON) D
ON capacitance		 VD = V+ or GND,
Switch ON,		 See Figure 15 25°C 2.5 V 24 pF
CI Digital input
capacitance		 VI = V+ or GND, See Figure 15 25°C 2.5 V 2 pF
BW Bandwidth RL = 50 Ω,
Switch ON,		 See Figure 17 25°C 2.5 V 165 MHz
OISO OFF isolation RL = 50 Ω,
f = 1 MHz,		 See Figure 18 25°C 2.5 V –69 dB
XTALK Crosstalk RL = 50 Ω,
f = 1 MHz,		 See Figure 19 25°C 2.5 V –69 dB
XTALK(ADJ) Crosstalk adjacent RL = 50 Ω,
f = 1 MHz,		 See Figure 20 25°C 2.5 V –74 dB
THD Total harmonic
distortion		 RL = 600 Ω,
CL = 50 pF,		 f = 20 Hz to 20 kHz,
see Figure 22 		25°C 2.5 V 0.29%
Supply
I+ Positive supply
current		 VI = V+ or GND, Switch ON or OFF 25°C 2.7 V 2.5 7 μA
Full 10
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(2) All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.