JAJSHA0E August 2011 – Oct 2019 TS3DS10224
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIK | Digital input clamp voltage | VCC = 3.6 V, II = –18 mA | –1.2 | –0.9 | V | |
IIN | Digital input leakage current | VCC = 3.6 V, VIN = 0 to 3.6 V | ±2 | µA | ||
IOZ | OFF-state leakage current(2) | VCC = 3.6 V, VO = 0 V to 3.6 V, VI = 0 V, Switch OFF | ±2 | µA | ||
IOFF | Power off leakage current | VCC = 0 V, VIN = VCC or GND,VIO = 0 V to 3.6 V | ±5 | µA | ||
ICC | Supply current | VCC = 3.6 V, IIO = 0, Switch ON or OFF | 50 | 100 | µA | |
CIN | Digital input capacitance | VCC = 3.3 V, VIN = VCC or GND | 3 | 5 | pF | |
CIO(OFF) | OFF capacitance | VCC = 3.3 V, VIO = 3.3 V or 0, f = 10 MHz, Switch OFF | 6 | 7 | pF | |
CIO(ON) | ON capacitance | VCC = 3.3 V, VIO = 3.3 V or 0, f = 10 MHz, Switch ON | 9 | 10 | pF | |
rON | ON-state resistance | VCC = 3.6 V, VI = VCC, IO = –30 mA | 13 | 19 | Ω | |
VCC = 3.3 V, VI = 0.5 V, IO = –30 mA | 10 | Ω | ||||
ΔrON | ON-state resistance match between channels | VCC = 3 V, VI = 0 to VCC, IO = –30 mA | 2 | 2.5 | Ω | |
rON(flat) | ON-state resistance flatness | VCC = 3 V, VI = 1.5 V and VCC, IO = –30 mA | 4 | 6 | Ω |