12.1 Layout Guidelines

• The thermal pad may be left floating or connected to the ground plane
• Place supply-bypass capacitors as close to the VCC pin as possible and avoid placing the bypass capacitors near the positive and negative traces.
• The high-speed positive and negative traces must always be matched and the lengths must not exceed 4 inches; otherwise, the eye diagram performance may be degraded. In layout, the impedance of positive and negative traces must match the cable characteristic differential impedance for optimal performance.
• Route the high-speed signals using a minimum of vias and corners to reduce signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended.
• When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
• Do not route signal traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals.
• Avoid stubs on the high-speed signal traces because they cause signal reflections.
• Route all high-speed signal traces over continuous GND planes, with no interruptions.
• Avoid crossing over anti-etch, commonly found with plane splits.
• Due to high-frequency signal traces, TI recommends a printed-circuit board with at least four layers; two signal layers separated by a ground and power layer as shown in Figure 24.

Figure 24. Four-Layer Board Stack-Up

The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.