SLLS783 Data sheet

SLLS783C May 2009 – March 2016 TSB81BA3E

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

ZAJ|168
- MPBG703D
PFP|80
- MPQF049B

サーマルパッド・メカニカル・データ

発注情報

slls783c_oa

8 Detailed Description

8.1 Overview

Data bits to be transmitted through the cable ports are received from the LLC on two-, four-, or eight-bit parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbits/s (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.

The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the P1394b standard.

The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a-2000 compliant device, the cable interface on that port operates in the 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b compliant node, the cable interface on that port operates per the P1394b standard at S400B or S800 speed. The TSB81BA3E automatically determines the correct cable interface connection method for the bilingual ports.

NOTE

The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When the BMODE terminal is deasserted, BOSS arbitration is disabled.

During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and active cable ports.

Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a-2000 compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage.

When connected to a 1394a-2000 compliant node, the TSB81BA3E provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 μF.

The line drivers in the TSB81BA3E are designed to work with external 112-Ω termination resistor networks to match the 110-Ω cable impedance. One termination network is required at each end of a twisted-pair cable. Each network is composed of a pair of series-connected ~56-Ω resistors. The midpoint of the pair of resistors that are connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that are directly connected to the TPB terminals is coupled to ground through a parallel RC network with recommended values of 5 kΩ and 270 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents.

When the power supply of the TSB81BA3E is off while the twisted-pair cables are connected, the TSB81BA3E transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at the other end of the cable.

When the TSB81BA3E is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the port must be forced to the 1394a-only mode (Data-Strobe-only mode), then the TPB+ and TPB– terminals can be tied together and then pulled to ground; or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS terminal can be connected to a 1-μF capacitor to ground or left unconnected.

To operate a port as a 1394b bilingual port, the force data-strobe-only terminal for the port (DS0, DS1, or DS2) needs to be pulled to ground through a 1-kΩ resistor. The port must be operated in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b beta-only connector is connected to the port. To operate the port as a 1394a-only port, the force data-strobe-only terminal (DS0, DS1, or DS2) needs to be pulled to 3.3 V V_CC through a 1-kΩ resistor. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6 pin, which is recommended, or 4 pin). This mode is provided to ensure that 1394b Signaling is never sent across a 1394a cable.

The TESTM, VREG_PD, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM and VREG_PD terminals must be connected to V_DD through a 1-kΩ resistor. The SE and SM terminals must be tied to ground through a 1-kΩ resistor.

Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They may be pulled high through a 1-kΩ resistor or hardwired low as a function of the equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB81BA3E, this bit may only be set by a write to the PHY register set. If a node desires to be a contender for IRM or BM, then the node software must set this bit in the PHY register set.

The LPS (link power status) terminal works with the LKON/DS2 terminal to manage the power usage in the node. The LPS signal from the LLC is used with the LCtrl bit (see Table 4 and Table 5 in the Application Information section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit).

The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB81BA3E detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB81BA3E continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB81BA3E issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible).

The PHY uses the LKON/DS2 terminal to notify the LLC to power up and become active. When activated, the output LKON/DS2 signal is a square wave. The PHY activates the LKON/DS2 output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the LKON/DS2 output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the LKON/DS2 output when a bus reset occurs, unless a PHY interrupt condition exists, which would otherwise cause LKON/DS2 to be active. If the PHY is power cycled and the power class is 0 through 4, then the PHY asserts LKON/DS2 for approximately 167 μs or until both the LPS is active and the LCTRL bit is 1.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 TTL Input Data

The data inputs to the transmitter come from the graphics processor and consist of up to 24 bits of video information, a horizontal synchronization bit, a vertical synchronization bit, an enable bit, and a spare bit. The data can be loaded into the registers upon either the rising or falling edge of the input clock selectable by the CLKSEL pin. Data inputs are 1.8 V to 3.3 V tolerant for the TSB81BA3E and can connect directly to low-power, low-voltage application and graphic processors. The bit mapping is listed in Table 1.

Table 1. Pixel Bit Ordering

	RED	GREEN	BLUE
LSB	R0	G0	B0
	R1	G1	B1
	R2	G2	B2
4-bit MSB	R3	G3	B3
	R4	G4	B4
6-bit MSB	R5	G5	B5
	R6	G6	B6
8-bit MSB	R7	G7	B7

8.3.2 LVDS Output Data

The pixel data assignment is listed in Table 2 for 24-bit, 18-bit, and 12-bit color hosts.

Table 2. Pixel Data Assignment

SERIAL CHANNEL	DATA BITS	8-BIT			6-BIT	4-BIT
SERIAL CHANNEL	DATA BITS	FORMAT-1	FORMAT-2	FORMAT-3		NON-LINEAR STEP SIZE	LINEAR STEP SIZE
Y0	D0	R0D27	R2	R2	R0	R2	VCC
	D1	R1	R3	R3	R1	R3	GND
	D2	R2	R4	R4	R2	R0	R0
	D3	R3	R5	R5	R3	R1	R1
	D4	R4	R6	R6	R4	R2	R2
	D6	R5	R7	R7	R5	R3	R3
	D7	G0	G2	G2	G0	G2	VCC
Y1	D8	G1	G3	G3	G1	G3	GND
	D9	G2	G4	G4	G2	G0	G0
	D12	G3	G5	G5	G3	G1	G1
	D13	G4	G6	G6	G4	G2	G2
	D14	G5	G7	G7	G5	G3	G3
	D15	B0	B2	B2	B0	B2	VCC
	D18	B1	B3	B3	B1	B3	GND
Y2	D19	B2	B4	B4	B2	B0	B0
	D20	B3	B5	B5	B3	B1	B1
	D21	B4	B6	B6	B4	B2	B2
	D22	B5	B7	B7	B5	B3	B3
	D24	HSYNC	HSYNC	HSYNC	HSYNC	HSYNC	HSYNC
	D25	VSYNC	VSYNC	VSYNC	VSYNC	VSYNC	VSYNC
	D26	ENABLE	ENABLE	ENABLE	ENABLE	ENABLE	ENABLE
Y3	D27	R6	R0	GND	GND	GND	GND
	D5	R7	R1	GND	GND	GND	GND
	D10	G6	G0	GND	GND	GND	GND
	D11	G7	G1	GND	GND	GND	GND
	D16	B6	B0	GND	GND	GND	GND
	D17	B7	B1	GND	GND	GND	GND
	D23	RSVD	RSVD	GND	GND	GND	GND
CLKOUT	CLKIN	CLK	CLK	CLK	CLK	CLK	CLK

8.4 Device Functional Modes

8.4.1 Input Clock Edge

The transmission of data bits D0 through D27 occurs as each are loaded into registers upon the edge of the CLKIN signal, where the rising or falling edge of the clock may be selected via CLKSEL. The selection of a clock rising edge occurs by inputting a high level to CLKSEL, which is achieved by populating pull-up resistor to pull CLKSEL=high. Inputting a low level to select a clock falling edge is achieved by directly connecting CLKSEL to GND.

8.4.2 Low Power Mode

The TSB81BA3E can be put in low-power consumption mode by active-low input SHTDN#. Connecting pin SHTDN# to GND will inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level. Populate a pull-up to VCC on SHTDN# to enable the device for normal operation.

8.4.3 1394b Port Interface Considerations

The TSB81BA3E has three 1394b cable ports that can operate at 100, 200, 400, or 800 Mbps. These ports are compliant with the IEEE Std 1394b-2002, standard. This section describes implementation considerations for the TSB81BA3E’s 1394b cable ports.

The cable not active (CNA) terminal is an output that reflects the state of the incoming 1394b cable port bias voltage. If no cable bias voltage is detected by the TSB81BA3E, then this output is asserted high. If the CNA terminal is not used, then it must be connected to GND through a 43-kΩ resistor.
The cable power status (CPS) terminal is an input that drives an internal comparator for the purpose of detecting the presence of 1394b cable power. Normally, terminal CPS is connected to the 1394b cable power source through a 390-kΩ resistor. However, if this detection feature is not used, then CPS should be connected directly to GND.
PC2, PC1, and PC0 are the power class programming inputs. These inputs are loaded into the power class field in the 1394b PHY base configuration registers. Since the binary value associated with the power class field is implementation specific, the system designer must reference the 1394b power class description table in the TSB81BA3E Data Manual to determine the appropriate PC2:0 input levels. Each terminal is connected to either GND or VDD_33 to specify the appropriate power class binary value. This connection may either be direct or through a weak resistor.
Terminals R0 and R1 are provided to set the operating current of the cable driver. A 6.34-kΩ ±1% resistor is required to meet the IEEE Std. output voltage limits. One side of the resistor is connected to the R0 terminal and the other side of the resistor to the R1 terminal. Signal traces must be short to minimize noise coupling into the two terminals.
TPAxP, TPAxN, TPBxP, TPBxN, and TPBIASx comprise the five major terminals associated with 1394b PHY port (Where x = Port#). TPAxP and TPAxN are the cable-A differential signals. TPBxP and TPBxN are the cable-B differential signals. TPBIASx provides the 1.86-V nominal bias required for proper 1394a driver/receiver operation and for active cable connection signaling to the remote node. The 1394b TPA and TPB differential pairs must follow the same routing guidelines as the PCI Express TX and RX differential pairs except for the differential impedance requirement of 110 ohms. For an unused port, all five terminals can be left as no connects. See the attached schematics for external circuit recommendations between the TSB81BA3E and 1394b cable connector.
The TSB81BA3E is designed to use an external 98.304-MHz crystal oscillator connected to the XI terminal to provide the reference clock. This clock, in turn, drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S800 media data rates.

8.5 Programming

8.5.1 Power-Class

The PC0-PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21−23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 3. The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4.

Table 3. Power-Class Descriptions

PC0-PC2	DESCRIPTION
000	Node does not need power and does not repeat power
001	Node is self-powered and provides a minimum of 15 W to the bus.
010	Node is self-powered and provides a minimum of 30 W to the bus.
011	Node is self-powered and provides a minimum of 45 W to the bus.
100	Node can be powered from the bus and is using up to 3 W; no additional power is needed to enable the link. The node can also provide power to the bus. The amount of bus power that it provides can be found in the configuration ROM.
101	Reserved for future standardization.
110	Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111	Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.

Figure 4. Typical TP Cable Connections

Figure 5. Typical DC-Isolated Outer Shield Termination

Figure 6. Non-DC-Isolated Outer Shield Termination

Figure 7. Nonisolated Connection Variations for LPS

Figure 8. Isolated Circuit Connection for LPS

8.6 Register Maps

8.6.1 Internal Register Configuration

There are 16 accessible internal registers in the TSB81BA3E. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which 1 of 8 pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. Note that while this register set is compatible with 1394a--2000 register sets, some fields have been redefined and this register set contains additional fields.

Table 4 shows the configuration of the base registers, and Table 5 gives the corresponding field descriptions. The base register field definitions are unaffected by the selected page number.

A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.

Table 4. Base Register Configuration

ADDRESS	BIT POSITION
ADDRESS	0	1	2	3	4	5	6	7
0000	Physical ID						R	CPS
0001	RHB	IBR	Gap_Count
0010	Extended (111b)			Num_Ports (0011b)
0011	PHY_Speed (111b)			SREN	Delay (1111b)
0100	LCtrl	C	Jitter (000b)			Pwr_Class
0101	WDIE	ISBR	CTOI	CPSI	STOI	PEI	EAA	EMC
0110	Max Legacy SPD			BLINK	Bridge		Rsvd
0111	Page_Select			Rsvd	Port_Select

Table 5. Base Register Field Descriptions

FIELD	SIZE	TYPE	DESCRIPTION
Physical ID	6	Rd	This field contains the physical address ID of this node determined during self-ID. The physical-ID is invalid after a bus reset until the self-ID has completed as indicated by an unsolicited register 0 status transfer from the PHY to the LLC.
R	1	Rd	Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1 during tree-ID if this node becomes root.
CPS	1	Rd	Cable-power status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to serial bus cable power through a 400-kΩ resistor. A 0 in this bit indicates that the cable-power voltage has dropped below its threshold for ensured reliable operation.
RHB	1	Rd/Wr	Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB bit is reset to 0 by a hardware reset and is unaffected by a bus reset. If two nodes on a single bus have their root holdoff bit set, then the result is not defined. To prevent two nodes from having their root-holdoff bit set, this bit must only be written using a PHY configuration packet.
IBR	1	Rd/Wr	Initiate bus reset. This bit instructs the PHY to initiate a long (166-μs) bus reset at the next opportunity. Any receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The IBR bit is reset to 0 after a hardware reset or a bus reset. Care must be exercised when writing to this bit to not change the other bits in this register. It is recommended that whenever possible a bus reset be initiated using the ISBR bit and not the IBR bit.
Gap_Count	6	Rd/Wr	Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet. The gap count is reset to 3Fh by hardware reset or after two consecutive bus resets without an intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet). It is strongly recommended that this field only be changed using PHY configuration packets.
Extended	3	Rd	Extended register definition. For the TSB81BA3E, this field is 111b, indicating that the extended register set is implemented.
Num_Ports	4	Rd	Number of ports. For the TSB81BA3E, this field indicates the number of ports implemented in the PHY. This field is 3.
PHY_Speed	3	Rd	PHY speed capability. For the TSB81BA3E, this field is no longer used. This field is 111b. Speeds for 1394b PHYs must be checked on a port-by-port basis.
Delay	4	Rd	PHY repeater data delay. This field indicates the worst-case repeater data delay of the PHY, expressed as 144+ (delay × 20) ns. For the TSB81BA3E, this field is 02h. This value is the repeater delay for the S400B case, which is slower than the S800B or 1394a cases. Since the IEEE 1394B−2002 Std Phy register set only has a single field for the delay parameter, the slowest value is used. If a network uses only S800B or 1394a connections, then a delay value of 00h may be used. The worst case Phy repeater delay is 197 ns for S400B and 127 ns for S800B cable speeds (trained, raw bit speed).
LCtrl	1	Rd/Wr	Link-active status control. This bit controls the indicated active status of the LLC reported in the self-ID packet. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC bit in the node self-ID packet is set active only if both the LPS input is active and the LCtrl bit is set. The LCtrl bit provides a software-controllable means to indicate the LLC self-ID active status in lieu of using the LPS input terminal. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset. NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received packets and status information continue to be presented on the interface, and any requests indicated on the LREQ input are processed, even if the LCtrl bit is cleared to 0.
C	1	Rd/Wr	Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to 0 on hardware reset. After hardware reset, this bit can only be set via a software register write. This bit is unaffected by a bus reset.
Jitter	3	Rd	PHY repeater jitter. This field indicates the worst-case difference between the fastest and slowest repeater data delay, expressed as (jitter+1) × 20 ns. For the TSB81BA3E, this field is 0.
Pwr_Class	3	Rd/Wr	Node power class. This field indicates this node power consumption and source characteristics and is replicated in the pwr field (bits 21–23) of the self-ID packet. This field is reset to the state specified by the PC0-PC2 input terminals upon a hardware reset, and is unaffected by a bus reset. See Table 3.
WDIE	1	Rd/Wr	Watchdog interrupt enable. This bit, if set to 1, enables the port event interrupt (PIE) bit to be set when resume operations begin on any port, or when any of the CTOI, CPSI, or STOI interrupt bits are set and the link interface is nonoperational. This bit is reset to 0 by hardware reset and is unaffected by bus reset.
ISBR	1	Rd/Wr	Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 μs) arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset. It is recommended that short bus reset is the only reset type initiated by software. IEC 61883-6 requires that a node initiate short bus resets to minimize any disturbance to an audio stream. NOTE: Legacy IEEE Std 1394-1995-compliant PHYs are not capable of performing short bus resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus reset being performed.
CTOI	1	Rd/Wr	Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID start and might indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset or by writing a 1 to this register bit. If the CTOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the LKON/DS2 output to notify the LLC to service the interrupt. NOTE: If the network is configured in a loop, then only those nodes that are part of the loop generate a configuration time-out interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus reset. This bit is only set when the bus topology includes 1394a nodes; otherwise, 1394b loop healing prevents loops from being formed in the topology.
CPSI	1	Rd/Wr	Cable power status interrupt. This bit is set to 1 when the CPS input transitions from high to low, indicating that cable power might be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be cleared by writing a 1 to this register bit. If the CPSI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the LKON/DS2 output to notify the LLC to service the interrupt.
STOI	1	Rd/Wr	State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset to occur). This bit is reset to 0 by hardware reset or by writing a 1 to this register bit. If the STOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the LKON/DS2 output to notify the LLC to service the interrupt.
PEI	1	Rd/Wr	Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for any port for which the port interrupt enable (PEI) bit is set. Additionally, if the resuming port interrupt enable (WDIE) bit is set, then the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit.
EAA	1	Rd/Wr	Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration enhancements defined in 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus reset. This bit has no effect when the device is operating in 1394b mode. NOTE: The use of accelerated arbitration is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. The EAA bit is set only if the attached LLC is 1394a-2000-compliant. If the LLC is not 1394a-2000 or 1394b-2002-compliant, then the use of the arbitration acceleration enhancements can interfere with isochronous traffic by excessively delaying the transmission of cycle-start packets.
EMC	1	Rd/Wr	Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of differing speeds in accordance with the protocols defined in 1394a-2000. This bit is reset to 0 by hardware reset and is unaffected by bus reset. This bit has no effect when the device is operating in 1394b mode. NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be 1394a-2000 or 1394b-2002-compliant.
Max Legacy SPD	3	Rd	Maximum legacy-path speed. This field holds the maximum speed capability of any legacy node (1394a-2000 or 1394-1995-compliant) as indicated in the self-ID packets received during bus initialization. Encoding is the same as for the PHY_SPEED field (but limited to S400 maximum).
BLINK	1	Rd	Beta-mode link. This bit indicates that a Beta-mode-capable link is attached to the PHY. This bit is set by the BMODE input terminal on the TSB81BA3E.
Bridge	2	Rd/Wr	This field controls the value of the bridge (brdg) field in self-ID packet. The power reset value is 0. Details for when to set these bits are specified in the IEEE 1394.1 bridging specification.
Page_Select	3	Rd/Wr	Page_Select. This field selects the register page to use when accessing register addresses 8 through 15. This field is reset to 0 by a hardware reset and is unaffected by bus reset.
Port_Select	4	Rd/Wr	Port_Select. This field selects the port when accessing per-port status or control (for example, when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by hardware reset and is unaffected by bus reset.

The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 6 shows the configuration of the port status page registers, and Table 7 gives the corresponding field descriptions. If the selected port is unimplemented, then all registers in the port status page are read as 0.

Table 6. Page 0 (Port Status) Register Configuration

ADDRESS	BIT POSITION
ADDRESS	0	1	2	3	4	5	6	7
1000	Astat		Bstat		Ch	Con	RxOK	Dis
1001	Negotiated_speed			PIE	Fault	Standby_fault	Disscrm	B_Only (0)
1010	DC_connected	Max_port_speed			LPP	Cable_speed
1011	Connection_unreliable	Reserved			Beta_mode	Reserved
1100	Port_error
1101	Reserved					Loop_disable	In_standby	Hard_disable
1110	Reserved
1111	Reserved

Table 7. Page 0 (Port Status) Register Field Descriptions

FIELD	SIZE	TYPE	DESCRIPTION
Astat	2	Rd	TPA line state. This field indicates the instantaneous TPA line state of the selected port, encoded as follows:
				Code	Arb Value
				11	Z
				01	1
				10	0
				00	invalid
Bstat	2	Rd	TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the Astat field.
Ch	1	Rd	Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid after a bus reset until tree-ID has completed.
Con	1	Rd	Debounced port connection status. This bit indicates that the selected port is connected. The connection must be stable for the debounce time of approximately 341 ms for the Con bit to be set to 1. The Con bit is reset to 0 by hardware reset and is unaffected by bus reset. NOTE: The Con bit indicates that the port is physically connected to a peer PHY, but this does not mean that the port is necessarily active. For 1394b-coupled connections, the Con bit is set when a port detects connection tones from the peer PHY and operating-speed negotiation is completed.
RxOK	1	Rd	Receive OK. In 1394a-2000 mode this bit indicates the reception of a debounced TPBias signal. In Beta mode, this bit indicates the reception of a continuous electrically valid signal. Note: RxOK is set to false during the time that only connection tones are detected in Beta mode.
Dis	1	Rd/Wr	Port disabled control. If this bit is 1, then the selected port is disabled. The Dis bit is reset to 0 by hardware reset (all ports are enabled for normal operation following hardware reset). The Dis bit is not affected by bus reset. When this bit is set, the port cannot become active; however, the port still tones, but does not establish an active connection.
Negotiated_speed	3	Rd	Indicates the maximum speed negotiated between this PHY port and its immediately connected port. The encoding is as for Max_port_speed. It is set during connection when in Beta mode or to a value established during self-ID when in 1394a-2000 mode.
PIE	1	Rd/Wr	Port-event-interrupt enable. When this bit is 1, a port event on the selected port sets the port-event-interrupt (PEI) bit and notifies the link. This bit is reset to 0 by a hardware reset and is unaffected by bus reset.
Fault	1	Rd/Wr	Fault. This bit indicates that a resume fault or suspend fault has occurred on the selected port, and that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. A suspend fault occurs when a suspending port continues to detect incoming cable bias from its attached peer. Writing 1 to this bit clears the Fault bit to 0. This bit is reset to 0 by hardware reset and is unaffected by bus reset.
Standby_fault	1	Rd/Wr	This bit is set to 1 if an error is detected during a standby operation and cleared on exit from the standby state. A write of 1 to this bit or receipt of the appropriate remote command packet clears it to 0. When this bit is cleared, standby errors are cleared.
Disscrm	1	Rd/Wr	Disable scrambler. If this bit is set to 1, then the data sent during packet transmission is not scrambled.
B_Only	1	Rd	Beta-mode operation only. For the TSB81BA3E, this bit is set to 0 for all ports.
DC_connected	1	Rd	If this bit is set to 1, the port has detected a dc connection to the peer port by means of a 1394a-style connect-detect circuit.
Max_port_speed	3	Rd/Wr	Max_port_speed The maximum speed at which a port is allowed to operate in Beta mode. The encoding is: 000 = S100 001 = S200 010 = S400 011 = S800 100 = S1600 101 = S3200 110 = reserved 111 = reserved An attempt to write to the register with a value greater than the hardware capability of the port results in the maximum value that the port is capable of being stored in the register. The port uses this register only when a new connection is established in the Beta mode or when a port is programmed as a Beta-only port. When a port is programmed as a bilingual port, it is fixed at S400 for the Beta speed and is not updated by a write to this register. The power reset value is the maximum speed capable of the port. Software can modify this value to force a port to train at a lower-than-maximum speed (when in a Beta-only mode), but no lower than the minimum speed.
LPP(Local_plug_ present)	1	Rd	This flag is set permanently to 1.
Cable_speed	3	Rd	This variable is set to the maximum speed that the port is capable of. The encoding is the same as for Max_port_speed.
Connection_ unreliable	1	Rd/Wr	If this bit is set to 1, then a Beta-mode speed negotiation has failed or synchronization has failed. A write of 1 to this field resets the value to 0.
Beta_mode	1	Rd	Operating in Beta mode. If this bit is 1, the port is operating in Beta mode; it is equal to 0 otherwise (that is, when operating in 1394a-2000 mode, or when disconnected). If Con is 1, RxOK is 1, and Beta_mode is 0, then the port is active and operating in the 1394a-2000 mode.
Port_error	8	Rd/Wr	Incremented when the port receives an invalid codeword, unless the value is already 255. Cleared when read (including being read by means of a remote access packet). Intended for use by a single bus-wide diagnostic program.
Loop_disable	1	Rd	This bit is set to 1 if the port has been placed in the loop-disable state as part of the loop-free build process (the PHYs at either end of the connection are active, but if the connection itself were activated, then a loop would exist). Cleared on bus reset and on disconnection.
In_standby	1	Rd	This bit is set to 1 if the port is in standby power-management state.
Hard_disable	1	Rd/Wr	No effect unless the port is disabled. If this bit is set to 1, the port does not maintain connectivity status on an ac connection when disabled. The values of the Con and RxOK bits are forced to 0. This flag can be used to force renegotiation of the speed of a connection. It can also be used to place the device into a lower-power state because when hard-disabled, a port no longer tones to maintain 1394b ac-connectivity status.

The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. Table 8 shows the configuration of the vendor identification page, and Table 9 shows the corresponding field descriptions.

Table 8. Page 1 (Vendor ID) Register Configuration

ADDRESS	BIT POSITION
ADDRESS	0	1	2	3	4	5	6	7
1000	Compliance
1001	Reserved
1010	Vendor_ID0
1011	Vendor_ID1
1100	Vendor_ID2
1101	Product_ID0
1110	Product_ID1
1111	Product_ID2

Table 9. Page 1 (Vendor ID) Register Field Descriptions

FIELD	SIZE	TYPE	DESCRIPTION
Compliance	8	Rd	Compliance level. For the TSB81BA3E, this field is 02h, indicating compliance with the 1394b-2002 specification.
Vendor_ID	24	Rd	Manufacturer's organizationally unique identifier (OUI). For the TSB81BA3E, this field is 08_00_28h (Texas Instruments) (the MSB is at register address 1010b).
Product_ID	24	Rd	Product identifier. For the TSB81BA3E, this field can be either 83_13_07h (the MSB is at register address 1101b).

The vendor-dependent page provides access to the special control features of the TSB81BA3E, as well as configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. Table 10 shows the configuration of the vendor-dependent page and Table 11 shows the corresponding field descriptions.

Table 10. Page 7 (Vendor-Dependent) Register Configuration

ADDRESS	BIT POSITION
ADDRESS	0	1	2	3	4	5	6	7
1000	Reserved						Reserved
1001	Reserved for test
1010	Reserved for test
1011	Reserved for test
1100	Reserved for test
1101	Reserved for test
1110	SWR	Reserved for test
1111	Reserved for test

Table 11. Page 7 (Vendor-Dependent) Register Field Descriptions

FIELD	SIZE	TYPE	DESCRIPTION
SWR	1	Rd/Wr	Software hard reset. Writing a 1 to this bit forces a hard reset of the PHY (same effect as momentarily asserting the RESET terminal low). This bit is always read as a 0.