SLVSC89A June   2014  – July 2014 TSC2013-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements — I2C Standard Mode (ƒ(SCL) = 100 kHz)
    7. 6.7  Timing Requirements — I2C Fast Mode (ƒ(SCL) = 400 kHz)
    8. 6.8  Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 1.7 MHz)
    9. 6.9  Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 3.4 MHz)
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Touch-Screen Operation
      2. 7.3.2 4-Wire Touch Screen Measurements
      3. 7.3.3 Analog-to-Digital Converter
        1. 7.3.3.1 Data Format
        2. 7.3.3.2 Reference
        3. 7.3.3.3 Variable Resolution
        4. 7.3.3.4 Conversion Clock and Conversion Time
        5. 7.3.3.5 Touch Detect
        6. 7.3.3.6 Preprocessing
          1. 7.3.3.6.1 Preprocessing—Median Value Filter and Averaging Value Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Controlled by TSC2013-Q1 and Initiated by TSC2013-Q1 (TSMode 1)
        1. 7.4.1.1 IX-IY Scan
        2. 7.4.1.2 X-Triplet, Y-Triplet, Z-Scan
      2. 7.4.2 Conversion Controlled by TSC2013-Q1 and Initiated by Host (TSMode 2)
      3. 7.4.3 Conversion Controlled by Host (TSMode 3)
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 I2C Fast or Standard Mode (F-S Mode)
        2. 7.5.1.2 I2C High-Speed Mode (Hs Mode)
      2. 7.5.2 Digital Interface
        1. 7.5.2.1 Address Byte
      3. 7.5.3 Control Byte
        1. 7.5.3.1 Touch-Screen Scan Function for XYZ or XY
      4. 7.5.4 Start a Write Cycle
      5. 7.5.5 Register Access
      6. 7.5.6 Communication Protocol
      7. 7.5.7 Register Reset
    6. 7.6 Register Maps
      1. 7.6.1 Register Content and Reset Values
      2. 7.6.2 Configuration and Status Registers
        1. 7.6.2.1 Configuration Register 0
          1. 7.6.2.1.1 Configuration Register 0 (address = 0) [reset = 4000h for read; 0000h for write]
        2. 7.6.2.2 Configuration Register 1 (address = Dh) [reset = 0000h]
        3. 7.6.2.3 Configuration Register 2 (address = Eh) [reset = 0000h]
        4. 7.6.2.4 Converter-Function Select Register (address = Fh) [reset = 0000h]
        5. 7.6.2.5 Status Register (address = 8h) [reset = 0004h]
      3. 7.6.3 Data Registers
        1. 7.6.3.1 X1, X2, IX, Y1, Y2, IY, Z1, Z2, and AUX registers (offset = see ) [reset = see ]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Auxiliary Measurement
      2. 8.1.2 Single IX or Single IY Measurement
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power-On-Reset and Reset Consideration
          1. 8.2.2.1.1 Power-On Reset
          2. 8.2.2.1.2 Requesting a Minimal t(SNSVDD_OFF) Time
          3. 8.2.2.1.3 Requesting a Minimal t(SNSVDD_OFF_ramp) and t(SNSVDD_ON_ramp) Ramp
          4. 8.2.2.1.4 Hardware Reset
          5. 8.2.2.1.5 Software Reset
        2. 8.2.2.2 Power Up Considerations
          1. 8.2.2.2.1 Power-Off Cycles During Normal Operation
          2. 8.2.2.2.2 Supply Glitches During Normal Operation
          3. 8.2.2.2.3 TSC2013-Q1 Digital Pins
          4. 8.2.2.2.4 Suggested Hardware Reset During Power-On
        3. 8.2.2.3 Device Timing Setup and Use
          1. 8.2.2.3.1 Touch-Panel Driving Power
          2. 8.2.2.3.2 ADC Clock Effects
        4. 8.2.2.4 Panel Voltage Stabilization Time
        5. 8.2.2.5 Precharge and Sense Time
        6. 8.2.2.6 Single-Touch Operation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range (unless otherwise noted).
MIN MAX UNIT
Voltage Analog input X+, Y+, AUX to SNSGND –0.4 SNSVDD + 0.1 V
Analog input X–, Y– to SNSGND –0.4 SNSVDD + 0.1 V
SNSVDD to SNSGND –0.3 5 V
SNSVDD to AGND –0.3 5 V
I/OVDD to AGND –0.3 5 V
SNSVDD to I/OVDD –2.4 0.3 V
Digital input voltage to AGND –0.3 I/OVDD + 0.3 V
Digital output voltage to AGND –0.3 I/OVDD + 0.3 V
Power dissipation (TJmax – TA) / RθJA
Operating free-air temperature range, TA –40 125 °C
Junction temperature, TJmax 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) –2000 2000 V
Charged device model (CDM), per AEC Q100-011 Corner pins (RSA: 1, 4, 5, 8, 9, 12, 13, and 16;
PW: 1, 8, 9, and 16)		 –750 750
Other pins –500 500
IEC contact discharge(2) X+, X–, Y+, Y– –15 15 kV
IEC air discharge(2) X+, X–, Y+, Y– –25 25 kV
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Test method based on IEC standard 61000-4-2. Contact Texas Instruments for test details.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage SNSVDD/VR 1.6 3.3 3.6 V
Input voltage I/OVDD 1.2 3.3 3.6 V

6.4 Thermal Information

THERMAL METRIC(1) RSA PW UNIT
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 33.7 100.9 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 36.7 36.1 °C/W
RθJB Junction-to-board thermal resistance 10.5 45.7 °C/W
ψJT Junction-to-top characterization parameter 0.6 2.6 °C/W
ψJB Junction-to-board characterization parameter 10.5 45.1 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 2.5 — °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At TA = –40°C to 125°C, V(SNSVDD/VREF) = 1.6 V to 3.6 V, and V(I/OVDD)(2) = 1.2 V to V(SNSVDD/VREF), unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUXILIARY ANALOG INPUT
Input voltage 0 Vref V
Input capacitance 12 pF
Input leakage current No ADC conversion –1 1 μA
Full-scale average input current V(SNSVDD/VREF) = 1.6 V, continuous AUX, ƒ(ADC) = 2 MHz 2 μA
ADC
Resolution Programmable: 10 or 12 bits 12 Bits
No missing codes 12-bit resolution 11 Bits
Integral linearity 12-bit resolution mode, ƒ(ADC) = 2 MHz –3 –0.5 to 0.5 3 LSB(1)
Differential linearity 12-bit resolution mode, fADC = 2MHz –2 –0.5 to 0.5 4 LSB
Offset error V(SNSVDD/VREF) = 1.6 V, 12-bit mode, ƒ(ADC) = 2 MHz, filter off 0.2 LSB
Gain error V(SNSVDD/VREF) = 1.6 V, 12-bit mode, ƒ(ADC) = 2 MHz, filter off 2 LSB
Data format Straight binary
REFERENCE INPUT
Vref range 1.6 V(SNSVDD/VREF) V
SNSVDD/VREF input-current drain Continuous AUX mode, V(SNSVDD/VREF) = 1.6 V, ƒ(ADC) = 2 MHz 5 μA
Input impedance No ADC conversion > 100 MΩ
TOUCH SENSORS
X+ 50-kΩ pullup resistor, R(IRQ) 52 kΩ
Switch on-resistance Y+, X+ TA = 25°C, V(SNSVDD/VREF) = 1.6 V 7 Ω
Y–, X– TA = 25°C, V(SNSVDD/VREF) = 1.6 V 5 Ω
Switch drivers drive current 100-ms duration 50 mA
INTERNAL OSCILLATOR
ƒ(OSC) Clock frequency V(SNSVDD/VREF) = 1.6 V, TA = 25°C 3.3 3.7 4.3 MHz
V(SNSVDD/VREF) = 3 V, TA = 25°C 3.8 MHz
Frequency drift V(SNSVDD/VREF) = 1.6 V –0.008 %/°C
V(SNSVDD/VREF) = 3 V –0.021 %/°C
DIGITAL INPUT/OUTPUT
Logic family CMOS
VIH Input-voltage logic-level high 1.2 V ≤ V(I/OVDD) < 3 V 0.7 × V(I/OVDD) 3.6 V
VIL Input-voltage logic-level low 1.2 V ≤ V(I/OVDD) < 3 V –0.3 0.2 × V(I/OVDD) V
IIL, IIH Input-current logic-level low and high –1 1 μA
CI Input-capacitance logic level 10 pF
VOH Output-voltage logic-level high IOH = 100 μA V(I/OVDD) – 0.2 V(I/OVDD) V
VOL Output-voltage logic-level low IOL = –3.2 mA 0 0.2 V
Ilkg Leakage-current logic level SDA –1 1 μA
CO Output-capacitance logic level SDA 10 pF
POWER-SUPPLY REQUIREMENTS
Power-supply voltage
SNSVDD 1.6 3 V
I/OVDD(2) 1.2 V(SNSVDD/VREF) V
Quiescent supply
current(3)(4)		 TA = 25°C, filter off, M = W = 1, C[3:0] = (1, 0, 0, 0), RM = 1, CL[1:0] = (0, 1), cont AUX mode, ƒ(ADC) = 2 MHz, without reading data register V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V 420 570 μA
TA = 25°C, filter on, M = 15, W = 7, PSM = 1, C[3:0] = (0, 0, 0, 0), RM = 1, CL[1:0] = (0, 1), BTD[2:0] = (1, 0, 1), 50 SSPS, MAVEX = MAVEY = MAVEZ = 1, ƒ(ADC) = 2 MHz, sensor drivers supply included(5) V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V 200 μA
V(SNSVDD/VREF) = V(I/OVDD) = 3 V 400 μA
TA = 25°C, filter off, M = W = 1, PSM = 1, C[3:0] = (0, 0, 0, 0), RM = 1, CL[1:0] = (0, 1), BTD[2:0] = (1, 0, 1), 50 SSPS, MAVEX = MAVEY = MAVEZ = 1, ƒ(ADC) = 2 MHz, sensor drivers supply included(5) V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V 180 μA
V(SNSVDD/VREF) = V(I/OVDD) = 3 V 370 μA
TA = 25°C, filter off, M = W = 1, C[3:0] = (0, 1, 0, 1), RM = 1, CL[1:0] = (0, 1), non-cont AUX mode, ƒ(ADC) = 2 MHz, high-speed mode V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V, approximately 28 kSPS effective rate 190 μA
V(SNSVDD/VREF) = V(I/OVDD) = 3 V, approximately 28.4 kSPS effective rate 370 μA
TA = 25°C, filter on, M = 7, W = 3, C[3:0] = (0, 1, 0, 1), RM = 1, CL[1:0] = (0, 1), MAVEAUX = 1, non-cont AUX mode, ƒ(ADC) = 2 MHz, high-speed mode, full speed V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V, approximately 10.5 kSPS effective rate 355 μA
V(SNSVDD/VREF) = V(I/OVDD) = 3 V, approximately 10.9 kSPS effective rate 655 μA
TA = 25°C, filter on, M = 7, W = 3, C[3:0] = (0, 1, 0, 1), RM = 1, CL[1:0] = (0, 1), MAVEAUX = 1, non-cont AUX mode, ƒ(ADC) = 2 MHz, high-speed mode, reduced speed (8.2-kSPS equivalent rate) V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V, approximately 1.17 kSPS effective rate 36.2 μA
V(SNSVDD/VREF) = V(I/OVDD) = 3 V, approximately 1.17 kSPS effective rate 64.9 μA
Power-down supply current TA = 25°C, not addressed, SCL = SDA = 1, RESET = 1,
PINTDAV = 1, V(SNSVDD/VREF) = I/OVDD = Vref = 1.6 V		 0.04 0.8 μA
Digital power-down supply current TA = 25°C, not addressed, SCL = SDA = 1, RESET = 1,
PINTDAV = 1, V(SNSVDD/VREF) = V(I/OVDD) = Vref = 1.6 V		 0.04 0.8 μA
(1) LSB means least-significant bit. With SNSVDD/VREF= 2.5 V, one LSB is 610 μV.
(2) I/OVDD must be ≤ SNSVDD.
(3) Supply current from SNSVDD.
(4) For detailed information on test condition parameter and bit settings, see the section.
(5) Touch sensor modeled by 2 kΩ for X– plane and Y– plane, and 1 kΩ for Z-plane (touch resistance).

6.6 Timing Requirements — I2C Standard Mode (ƒ(SCL) = 100 kHz)

All specifications typical at –40°C to 125°C, V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V to 3 V, unless otherwise noted.
MIN MAX UNIT
t(WL_RESET) Reset low time(1) See Figure 1 and Figure 37 10 μs
ƒ(SCL) SCL clock frequency 100 kHz
t(BUF) Bus free time between a STOP and START condition See Figure 1 4.7 μs
th(STA) Hold time for (repeated) START condition 4 μs
t(LOW) Low period of SCL clock 4.7 μs
t(HIGH) High period of the SCL clock 4 μs
tsu(STA) Setup time for a repeated START condition 4.7 μs
th(DAT) Data hold time 0 3.45 μs
tsu(DAT) Data setup time 250 ns
tr Rise time of both SDA and SCL signals C(b) = total bus capacitance
See Figure 1		 1000 ns
tf Fall time of both SDA and SCL signals 300 ns
tsu(STO) Setup time for STOP condition See Figure 1 4 μs
C(b) Capacitive load for each bus line C(b) = total capacitance of one bus line in pF 400 pF
td(SP) Pulse duration of spikes that must be suppressed by the input filter N/A N/A ns
(1) V(SNSVDD/VREF) ≥ 1.6 V

6.7 Timing Requirements — I2C Fast Mode (ƒ(SCL) = 400 kHz)

All specifications typical at –40°C to 125°C, V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V to 3 V, unless otherwise noted.
MIN MAX UNIT
t(WL_RESET) Reset low time(2) See Figure 1 and Figure 37 10 μs
ƒ(SCL) SCL clock frequency 400 kHz
t(BUF) Bus free time between a STOP and START condition See Figure 1 1.3 μs
th(STA) Hold time for (repeated) START condition 0.6 μs
t(LOW) Low period of SCL clock 1.3 μs
t(HIGH) High period of the SCL clock 0.6 μs
tsu(STA) Setup time for a repeated START condition 0.6 μs
th(DAT) Data hold time 0 0.9 μs
tsu(DAT) Data setup time 100 ns
tr Rise time of both SDA and SCL signals C(b) = total bus capacitance
See Figure 1		 20 + 0.1 × C(b) 300 ns
tf Fall time of both SDA and SCL signals(1) 20 + 0.1 × C(b) 300 ns
tsu(STO) Setup time for STOP condition See Figure 1 0.6 μs
C(b) Capacitive load for each bus line C(b) = total capacitance of one bus line in pF 400 pF
td(SP) Pulse duration of spikes that must be suppressed by the input filter 0 50 ns
(1) C(b) = the total capacitance of one bus line in pF. If using both fast-mode and Hs-mode devices, one may use faster fall times according to the Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 3.4 MHz) section. Note that the TSC2013-Q1 device is an Hs-mode device and follows the table requirements listed in the Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 3.4 MHz) section.
(2) V(SNSVDD/VREF) ≥ 1.6 V

6.8 Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 1.7 MHz)

All specifications typical at –40°C to 125°C, V(SNSVDD/VREF) = V(I/OVDD) = to 3 V, unless otherwise noted.
MIN MAX UNIT
t(WL_RESET) Reset low time(2) See Figure 2 and Figure 37 10 μs
ƒ(SCL) SCL clock frequency 1.7 MHz
th(STA) Hold time of (repeated) START condition See Figure 2 160 ns
t(LOW) Low period of SCL clock 320 ns
t(HIGH) High period of the SCL clock 120 ns
tsu(STA) Setup time for a repeated START condition 160 ns
th(DAT) Data hold time 0 150 ns
tsu(DAT) Data setup time 10 ns
tr(CL) Rise time of SCL signal C(b) = total bus capacitance(1)
Figure 2		 20 80 ns
tr(DA) Rise time of SDA signal 20 160 ns
tf(CL) Fall time of SCL signal 20 80 ns
tf(DA) Fall time of SDA signal 1 160 ns
tr(CL1) Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 160 ns
tsu(STO) Setup time for STOP condition See Figure 2 160 ns
C(b) Capacitive load for each bus line C(b) = total capacitance of one bus line in pF 400 pF
td(SP) Pulse duration of spikes that must be suppressed by the input filter 0 10 ns
(1) For capacitive bus loads between 100 pF and 400 pF, interpolate the rise-time and fall-time values linearly.
(2) V(SNSVDD/VREF) ≥ 1.6 V

6.9 Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 3.4 MHz)

All specifications typical at –40°C to 125°C, V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V(1) to 3 V, unless otherwise noted.
MIN MAX UNIT
t(WL_RESET) Reset low time(3) See Figure 2 and Figure 37 10 μs
ƒ(SCL) SCL clock frequency 3.4 MHz
th(STA) Hold time for (repeated) START condition See Figure 2 160 ns
t(LOW) Low period of SCL clock 160 ns
t(HIGH) High period of the SCL clock 60 ns
tsu(STA) Setup time for a repeated START condition 160 ns
th(DAT) Data hold time 0 70 ns
tsu(DAT) Data setup time 10 ns
tr(CL) Rise time of SCL signal C(b) = total bus capacitance(2)
See Figure 2		 10 40 ns
tr(DA) Rise time of SDA signal 10 80 ns
tf(CL) Fall time of SCL signal 10 40 ns
tf(DA) Fall time of SDA signal 1 80 ns
tr(CL1) Rise time of SCL signal after a repeated START condition and after an acknowledge bit 10 80 ns
tsu(STO) Setup time for STOP condition See Figure 2 160 ns
C(b) Capacitive load for each bus line C(b) = total capacitance of one bus line in pF 100 pF
td(SP) Pulse duration of spikes that must be suppressed by the input filter 0 10 ns
(1) Because of the low supply voltage of 1.2 V and the wide temperature range of –40°C to 125°C, the I2C system devices may not reach the maximum specification of I2C high-speed mode, and ƒ(SCL) may not reach 3.4 MHz.
(2) Capacitive load from 10 pF to 100 pF.
(3) V(SNSVDD/VREF) ≥ 1.6 V
timing1_std_slvsc89.gifFigure 1. Detailed I/O Timing for Standard and Fast Modes
timing2_hs_slvsc89.gif
1. The First rising edge of the SCL signal after Sr and after each acknowledge bit.
Figure 2. Detailed I/O Timing for High-Speed Mode

6.10 Typical Characteristics

At TA = –40°C to 125°C, SNSVDD/VREF = 1.6 V to 3 V, I/OVDD = 1.2 V to SNSVDD/VREF, ƒ(ADC) = ƒ(OSC) / 2, high-speed mode (ƒ(SCL) = 3.4 MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
tc_offset_change_temp_slvsc89.gifFigure 3. Change in Offset vs Temperature
tc_vdd_isupply_temp_slvsc89.gif
M = 1 W = 1 (See Table 1) ƒ(SAMPLE) = 28 kHz
AUX non-continuous mode
Figure 5. SNSVDD Supply Current vs Temperature
tc_vdd_isupply_vsupply02_slvsc89.gif
t(PVS), t(PRE), t(SNS) = default values
TSC-initiated mode scan X, Y, and Z at 50SSPS
Touch sensor modeled by: 2 kΩ for X-plane and Y-plane and 1 kΩ for Z (touch resistance, See Figure 14)
Figure 7. Supply Current vs Supply Voltage, TA = 25° C
tc_pd_isupply_vdd_slvsc89.gif
TA = 25°C
Figure 9. Power-Down Supply Current vs Supply Voltage
tc_iovdd_isupply_vdd_slvsc89.gif
IOVDD = SNSVDD/VREF ƒ(SAMPLE) = 28 kHz
Figure 11. I/OVDD Supply Current vs I/OVDD Supply Voltage
tc_ref_input_current_vsupply_slvsc89.gif
IOVDD = SNSVDD/VREF AUX continuous mode
TA = 25°C
Figure 13. Reference Input Current vs SNSVDD Supply Voltage
tc_gain_change_temp_slvsc89.gifFigure 4. Change in Gain vs Temperature
tc_vdd_isupply_vsupply01_slvsc89.gif
TA = 25° C
Figure 6. SNSVDD Supply Current vs SNSVDD Supply Voltage
tc_pd_isupply_temp_slvsc89.gif
Figure 8. Power-Down Supply Current vs Temperature
tc_iovdd_isupply_temp_slvsc89.gif
I/OVDD = SNSVDD/VREF
Figure 10. I/OVDD Supply Current vs Temperature
tc_ref_input_current_temp_slvsc89.gif
IOVDD = SNSVDD/VREF AUX continuous mode
Figure 12. Reference Input Current vs Temperature