JAJSLG0B April   2021  – March 2023 TSER953

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended Timing for the Serial Control Bus
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CSI-2 Receiver
        1. 7.3.1.1 CSI-2 Receiver Operating Modes
        2. 7.3.1.2 CSI-2 Receiver High-Speed Mode
        3. 7.3.1.3 CSI-2 Protocol Layer
        4. 7.3.1.4 CSI-2 Short Packet
        5. 7.3.1.5 CSI-2 Long Packet
        6. 7.3.1.6 CSI-2 Errors and Detection
          1. 7.3.1.6.1 CSI-2 ECC Detection and Correction
          2. 7.3.1.6.2 CSI-2 Check Sum Detection
          3. 7.3.1.6.3 D-PHY Error Detection
          4. 7.3.1.6.4 CSI-2 Receiver Status
      2. 7.3.2 V3Link Forward Channel Transmitter
        1. 7.3.2.1 Frame Format
      3. 7.3.3 V3Link Back Channel Receiver
      4. 7.3.4 Serializer Status and Monitoring
        1. 7.3.4.1 Forward Channel Diagnostics
        2. 7.3.4.2 Back Channel Diagnostics
        3. 7.3.4.3 Voltage and Temperature Sensing
          1. 7.3.4.3.1 Programming Example
        4. 7.3.4.4 Built-In Self Test
      5. 7.3.5 FrameSync Operation
        1. 7.3.5.1 External FrameSync
        2. 7.3.5.2 Internally Generated FrameSync
      6. 7.3.6 GPIO Support
        1. 7.3.6.1 GPIO Status
        2. 7.3.6.2 GPIO Input Control
        3. 7.3.6.3 GPIO Output Control
        4. 7.3.6.4 Forward Channel GPIO
        5. 7.3.6.5 Back Channel GPIO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clocking Modes
        1. 7.4.1.1 Synchronous Mode
        2. 7.4.1.2 Non-Synchronous Clock Mode
        3. 7.4.1.3 Non-Synchronous Internal Mode
        4. 7.4.1.4 DVP Compatibility Mode
        5. 7.4.1.5 Configuring CLK_OUT
      2. 7.4.2 MODE
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Configuration
        1. 7.5.1.1 CLK_OUT/IDX
          1. 7.5.1.1.1 IDX
      2. 7.5.2 I2C Interface Operation
      3. 7.5.3 I2C Timing
    6. 7.6 Pattern Generation
      1. 7.6.1 Reference Color Bar Pattern
      2. 7.6.2 Fixed Color Patterns
      3. 7.6.3 Packet Generator Programming
        1. 7.6.3.1 Determining Color Bar Size
      4. 7.6.4 Code Example for Pattern Generator
    7. 7.7 Register Maps
      1. 7.7.1   I2C Device ID Register
      2. 7.7.2   Reset
      3. 7.7.3   General Configuration
      4. 7.7.4   Forward Channel Mode Selection
      5. 7.7.5   BC_MODE_SELECT
      6. 7.7.6   PLL Clock Control
      7. 7.7.7   Clock Output Control 0
      8. 7.7.8   Clock Output Control 1
      9. 7.7.9   Back Channel Watchdog Control
      10. 7.7.10  I2C Control 1
      11. 7.7.11  I2C Control 2
      12. 7.7.12  SCL High Time
      13. 7.7.13  SCL Low Time
      14. 7.7.14  Local GPIO DATA
      15. 7.7.15  GPIO Input Control
      16. 7.7.16  RESERVED Register
      17. 7.7.17  DVP_CFG
      18. 7.7.18  DVP_DT
      19. 7.7.19  RESERVED Register
      20. 7.7.20  Force BIST Error
      21. 7.7.21  Remote BIST Control
      22. 7.7.22  Sensor Voltage Gain
      23. 7.7.23  RESERVED Register
      24. 7.7.24  Sensor Control 0
      25. 7.7.25  Sensor Control 1
      26. 7.7.26  Voltage Sensor 0 Thresholds
      27. 7.7.27  Voltage Sensor 1 Thresholds
      28. 7.7.28  Temperature Sensor Thresholds
      29. 7.7.29  CSI-2 Alarm Enable
      30. 7.7.30  Alarm Sense Enable
      31. 7.7.31  Back Channel Alarm Enable
      32. 7.7.32  RESERVED Register
      33. 7.7.33  CSI-2 Polarity Select
      34. 7.7.34  CSI-2 LP Mode Polarity
      35. 7.7.35  CSI-2 High-Speed RX Enable
      36. 7.7.36  CSI-2 Low Power Enable
      37. 7.7.37  CSI-2 Termination Enable
      38. 7.7.38  RESERVED Register
      39. 7.7.39  RESERVED Register
      40. 7.7.40  RESERVED Register
      41. 7.7.41  RESERVED Register
      42. 7.7.42  RESERVED Register
      43. 7.7.43  RESERVED Register
      44. 7.7.44  RESERVED Register
      45. 7.7.45  RESERVED Register
      46. 7.7.46  CSI-2 Packet Header Control
      47. 7.7.47  Back Channel Configuration
      48. 7.7.48  Datapath Control 1
      49. 7.7.49  RESERVED Register
      50. 7.7.50  Remote Partner Capabilities 1
      51. 7.7.51  RESERVED Register
      52. 7.7.52  Partner Deserializer ID
      53. 7.7.53  RESERVED Register
      54. 7.7.54  Target 0 ID
      55. 7.7.55  Target 1 ID
      56. 7.7.56  Target 2 ID
      57. 7.7.57  Target 3 ID
      58. 7.7.58  Target 4 ID
      59. 7.7.59  Target 5 ID
      60. 7.7.60  Target 6 ID
      61. 7.7.61  Target 7 ID
      62. 7.7.62  Target 0 Alias
      63. 7.7.63  Target 1 Alias
      64. 7.7.64  Target 2 Alias
      65. 7.7.65  Target 3 Alias
      66. 7.7.66  Target 4 Alias
      67. 7.7.67  Target 5 Alias
      68. 7.7.68  Target 6 Alias
      69. 7.7.69  Target 7 Alias
      70. 7.7.70  Back Channel Control
      71. 7.7.71  Revision ID
      72. 7.7.72  Device Status
      73. 7.7.73  General Status
      74. 7.7.74  GPIO Pin Status
      75. 7.7.75  BIST Error Count
      76. 7.7.76  CRC Error Count 1
      77. 7.7.77  CRC Error Count 2
      78. 7.7.78  Sensor Status
      79. 7.7.79  Sensor V0
      80. 7.7.80  Sensor V1
      81. 7.7.81  Sensor T
      82. 7.7.82  RESERVED Register
      83. 7.7.83  CSI-2 Error Count
      84. 7.7.84  CSI-2 Error Status
      85. 7.7.85  CSI-2 Errors Data Lanes 0 and 1
      86. 7.7.86  CSI-2 Errors Data Lanes 2 and 3
      87. 7.7.87  CSI-2 Errors Clock Lane
      88. 7.7.88  CSI-2 Packet Header Data
      89. 7.7.89  Packet Header Word Count 0
      90. 7.7.90  Packet Header Word Count 1
      91. 7.7.91  CSI-2 ECC
      92. 7.7.92  RESERVED Register
      93. 7.7.93  RESERVED Register
      94. 7.7.94  RESERVED Register
      95. 7.7.95  RESERVED Register
      96. 7.7.96  RESERVED Register
      97. 7.7.97  RESERVED Register
      98. 7.7.98  RESERVED Register
      99. 7.7.99  RESERVED Register
      100. 7.7.100 RESERVED Register
      101. 7.7.101 RESERVED Register
      102. 7.7.102 RESERVED Register
      103. 7.7.103 RESERVED Register
      104. 7.7.104 RESERVED Register
      105. 7.7.105 RESERVED Register
      106. 7.7.106 RESERVED Register
      107. 7.7.107 RESERVED Register
      108. 7.7.108 RESERVED Register
      109. 7.7.109 RESERVED Register
      110. 7.7.110 RESERVED Register
      111. 7.7.111 RESERVED Register
      112. 7.7.112 RESERVED Register
      113. 7.7.113 RESERVED Register
      114. 7.7.114 RESERVED Register
      115. 7.7.115 RESERVED Register
      116. 7.7.116 RESERVED Register
      117. 7.7.117 RESERVED Register
      118. 7.7.118 RESERVED Register
      119. 7.7.119 RESERVED Register
      120. 7.7.120 RESERVED Register
      121. 7.7.121 RESERVED Register
      122. 7.7.122 RESERVED Register
      123. 7.7.123 IND_ACC_CTL
      124. 7.7.124 IND_ACC_ADDR
      125. 7.7.125 IND_ACC_DATA
      126. 7.7.126 RESERVED Register
      127. 7.7.127 V3LINK_TX_ID0
      128. 7.7.128 V3LINK_TX_ID1
      129. 7.7.129 V3LINK_TX_ID2
      130. 7.7.130 V3LINK_TX_ID3
      131. 7.7.131 V3LINK_TX_ID4
      132. 7.7.132 V3LINK_TX_ID5
      133. 7.7.133 Indirect Access Registers
        1. 7.7.133.1  Reserved
        2. 7.7.133.2  PGEN_CTL
        3. 7.7.133.3  PGEN_CFG
        4. 7.7.133.4  PGEN_CSI_DI
        5. 7.7.133.5  PGEN_LINE_SIZE1
        6. 7.7.133.6  PGEN_LINE_SIZE0
        7. 7.7.133.7  PGEN_BAR_SIZE1
        8. 7.7.133.8  PGEN_BAR_SIZE0
        9. 7.7.133.9  PGEN_ACT_LPF1
        10. 7.7.133.10 PGEN_ACT_LPF0
        11. 7.7.133.11 PGEN_TOT_LPF1
        12. 7.7.133.12 PGEN_TOT_LPF0
        13. 7.7.133.13 PGEN_LINE_PD1
        14. 7.7.133.14 PGEN_LINE_PD0
        15. 7.7.133.15 PGEN_VBP
        16. 7.7.133.16 PGEN_VFP
        17. 7.7.133.17 PGEN_COLOR0
        18. 7.7.133.18 PGEN_COLOR1
        19. 7.7.133.19 PGEN_COLOR2
        20. 7.7.133.20 PGEN_COLOR3
        21. 7.7.133.21 PGEN_COLOR4
        22. 7.7.133.22 PGEN_COLOR5
        23. 7.7.133.23 PGEN_COLOR6
        24. 7.7.133.24 PGEN_COLOR7
        25. 7.7.133.25 PGEN_COLOR8
        26. 7.7.133.26 PGEN_COLOR9
        27. 7.7.133.27 PGEN_COLOR10
        28. 7.7.133.28 PGEN_COLOR11
        29. 7.7.133.29 PGEN_COLOR12
        30. 7.7.133.30 PGEN_COLOR13
        31. 7.7.133.31 PGEN_COLOR14
        32. 7.7.133.32 PGEN_COLOR15
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power-over-Coax
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 CSI-2 Interface
        2. 8.2.2.2 V3Link Input / Output
        3. 8.2.2.3 Internal Regulator Bypassing
        4. 8.2.2.4 Loop Filter Decoupling
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
      1. 9.1.1 System Initialization
    2. 9.2 Power Down (PDB)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CSI-2 Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.1 Power-over-Coax

The TSER953 is designed to support the Power-over-Coax (PoC) method of powering remote sensor systems. With this method, the power is delivered over the same medium (a coaxial cable) used for high-speed digital video data, bidirectional control, and diagnostics data transmission. This method uses passive networks or filters that isolate the transmission line from the loading of the DC-DC regulator circuits and their connecting power traces on both sides of the link as shown in Figure 8-1.

GUID-20210324-CA0I-Q8FL-VQB8-TZRBZXWHXRB1-low.svg Figure 8-1 Power-over-Coax (PoC) System Diagram

The PoC networks' impedance of ≥ 1 kΩ over a specific frequency band is recommended to isolate the transmission line from the loading of the regulator circuits. Higher PoC network impedance will contribute to favorable insertion loss and return loss characteristics in the high-speed channel. The lower limit of the frequency band is defined as ½ of the frequency of the bidirectional control channel, fBCC. The upper limit of the frequency band is the frequency of the forward high-speed channel, fFC. However, the main criteria that need to be met in the total high-speed channel, which consists of a serializer PCB, a deserializer PCB, and a cable, are the insertion loss and return loss limits defined in the Total Channel Requirements(1) over the entire system, while the system is under maximum current load and extreme temperature conditions (2).

  1. Contact TI for more information on the required Channel Specifications defined for each individual V3Link device.
  2. The PoC network and any components along the high-speed trace on the PCB will contribute to the PCB loss budget. TI has recommendations for the loss budget allocation for each individual PCB and cable component in the overall high-speed channel, but the loss limits defined for the total channel in the Channel Specifications must be met.
Figure 8-2 shows an example PoC network suitable for a "4G" V3Link consisting of TSER953 and TDES954 or TDES960 pair with the bidirectional channel operating at 50 Mbps (½ fBCC = 25 MHz) and the forward channel operating at 4.16 Gbps (fFC ≈ 2.1 GHz). Other PoC networks are possible and may be different on the serializer and the deserializer boards as long as the printed-circuit board channel specifications are met.
GUID-EBB058FF-32E5-4BF8-900E-0157C597E370-low.gif Figure 8-2 Typical PoC Network for a "4G" V3Link

Table 8-1 lists essential components for this particular PoC network. Note that the impedance characteristic of the ferrite beads deviates with the bias current. Therefore, keeping the current going through the network below 150 mA is recommended.

Table 8-1 Suggested Components for a "4G" V3Link PoC Network
COUNT REF DES DESCRIPTION PART NUMBER MFR
1 L1 Inductor, 10 µH, 0.288 Ω maximum, 530 mA minimum (Isat, Itemp)
30 MHz SRF minimum, 3 mm × 3 mm, General-Purpose		 LQH3NPN100MJR Murata
Inductor, 10 µH, 0.288 Ω maximum, 530 mA minimum (Isat, Itemp)
30 MHz SRF minimum, 3 mm × 3 mm, AEC-Q200		 LQH3NPZ100MJR Murata
Inductor, 10 µH, 0.360 Ω maximum, 450 mA minimum (Isat, Itemp)
30 MHz SRF minimum, 3.2 mm × 2.5 mm, AEC-Q200		 NLCV32T-100K-EFD TDK
Inductor, 10 µH, 0.400 Ω typical, 550 mA minimum (Isat, Itemp)
39 MHz SRF typical, 3 mm × 3 mm, AEC-Q200		 TYS3010100M-10 Laird
Inductor, 10 µH, 0.325 Ω maximum, 725 mA minimum (Isat, Itemp)
41 MHz SRF typical, 3 mm × 3 mm, AEC-Q200		 TYS3015100M-10 Laird
3 FB1-FB3 Ferrite Bead, 1.5 kΩ at 1 GHz, 0.5 Ω maximum at DC
500 mA at 85°C, 0603 SMD , General-Purpose		 BLM18HE152SN1 Murata
Ferrite Bead, 1.5 kΩ at 1 GHz, 0.5 Ω maximum at DC
500 mA at 85°C, 0603 SMD , AEC-Q200		 BLM18HE152SZ1 Murata

In addition to the selection of PoC network components, their placement and layout play a critical role as well.

  • Place the smallest component, typically a ferrite bead or a chip inductor, as close to the connector as possible. Route the high-speed trace through one of its pads to avoid stubs.
  • Use the smallest component pads as allowed by manufacturer's design rules. Add anti-pads in the inner planes below the component pads to minimize impedance drop.
  • Consult with the connector manufacturer for optimized connector footprint. If the connector is mounted on the same side as the IC, minimize the impact of the through-hole connector stubs by routing the high-speed signal traces on the opposite side of the connector mounting side.
  • Use coupled 100-Ω differential signal traces from the device pins to the AC-coupling caps. Use 50-Ω single-ended traces from the AC-coupling capacitors to the connector.
  • Terminate the inverting signal traces close to the connectors with standard 49.9-Ω resistors.

The suggested characteristics for single-ended PCB traces (microstrips or striplines) for serializer or deserializer boards are listed in Table 8-2. The effects of the PoC networks must be accounted for when testing the traces for compliance to the suggested limits.

Table 8-2 Suggested Characteristics for Single-Ended PCB Traces With Attached PoC Networks
PARAMETER MIN TYP MAX UNIT
Ltrace Single-ended PCB trace length from the device pin to the connector pin 5 cm
Ztrace Single-ended PCB trace characteristic impedance 45 50 55 Ω
Zcon Connector (mounted) characteristic impedance 40 50 60 Ω

The VPOC fluctuations on the serializer side, caused by the transient current draw of the sensor, the DC resistance of cables, and PoC components, must be kept to a minimum as well. Increasing the VPOC voltage and adding extra decoupling capacitance (> 10 µF) help reduce the amplitude and slew rate of the VPOC fluctuations.