JAJSQI5B June   2023  – October 2023 TSM24CA-Q1

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - AEC Specifications
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 ESD Ratings - ISO Specifications
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7Application and Implementation
    1. 7.1 Application Information
  9. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBZ|3
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 100 nA -24 24 V
ILEAK Leakage current at VRWM VIO = 24 V, I/O to GND & GND to I/O 25 75 nA
VBR Breakdown voltage, I/O to GND & GND to I/O (1) IIO = 10 mA 25.5 V
VCLAMP Surge clamping voltage, tp = 8/20 µs (3) IPP = 24A, I/O to GND & GND to I/O 40 V
CLINE Line capacitance, IO to GND VIO = 0 V, f = 1 MHz 12 pF
(1) VBR is defined as the voltage obtained at 10 mA when sweeping the voltage up, before the device latches into the snapback state
(2) Device stressed with 8/20 µs exponential decay waveform according to IEC 61000-4-5