TSV91x レール・ツー・レール入出力、8MHzオペアンプ
- JAJSDM4D July 2017 – October 2019 TSV911 , TSV912 , TSV914
  
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TSV91x レール・ツー・レール入出力、8MHzオペアンプ

このリソースの元の言語は英語です。翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

レール・ツー・レールの入出力
低ノイズ：18nV/√Hz (1kHz 時)
低い消費電力：550µA (標準値)
高いゲイン帯域幅：8MHz
動作電源電圧範囲：2.5V～5.5V
低い入力バイアス電流：1pA (標準値)
低い入力オフセット電圧：1.5mV (最大値)
低いオフセット電圧ドリフト係数：±0.5µV/℃ (標準値)
内部 ESD 保護：人体モデル (HBM) ±4kV
拡張温度範囲：–40℃～125℃

2 アプリケーション

バッテリ駆動のアプリケーション
モータ制御
パワー・モジュール
HVAC：暖房、換気、および空調
洗濯機
冷蔵庫
医療用計測装置
アクティブ・フィルタ
センサ信号コンディショニング
オーディオ・レシーバ
車載インフォテインメント

3 概要

TSV91xファミリにはシングル、デュアル、クワッド・チャネルのオペアンプが含まれ、汎用アプリケーション向けに特化して設計されています。このファミリは、レール・ツー・レールの入出力(RRIO)スイング、広い帯域幅(8MHz)、低いオフセット電圧(標準値0.3mV)の特長を持ち、速度と消費電力との適切なバランスを必要とする各種のアプリケーション向けに設計されています。オペアンプはユニティ・ゲイン安定で、入力バイアス電流が非常に低い特長があるため、このファミリは高いソース・インピーダンスのアプリケーションに使用できます。入力バイアス電流が低いため、センサ・インターフェイス、バッテリ電源および携帯型アプリケーション、アクティブ・フィルタにデバイスを使用できます。

TSV91xは堅牢な設計のため、回路設計者が簡単に使用できます。ユニティ・ゲイン安定、RFI-EMI除去フィルタの内蔵、オーバードライブ状況で位相反転が発生しない、高い静電放電(ESD)保護(4kV HBV)などの特長があります。

製品情報⁽¹⁾

型番	パッケージ	本体サイズ（公称）
TSV911	SOT-23 (5)	1.60mm × 2.90mm
TSV911	SC70 (5)	1.25mm×2.00mm
TSV912	SOIC (8)	3.91mm×4.90mm
	WSON (8)	2.00mm×2.00mm
	SOT-23 (8)	1.60mm × 2.90mm
TSV914	SOIC (14)	8.65mm×3.91mm
TSV914	TSSOP (14)	4.40mm×5.00mm

提供されているすべてのパッケージについては、データシートの末尾にある注文情報を参照してください。

Device Images

ローサイドのモータ制御

小信号のオーバーシュートと負荷容量との関係

4 改訂履歴

Changes from C Revision (January 2019) to D Revision

Added データシートに SOT-23 (8) (DDF) パッケージ情報をGo

Changes from B Revision (April 2018) to C Revision

Deleted TSV911IDBV のプレビュー版表記をGo
Added 「製品情報」表に SC70 パッケージ情報をGo
Deleted package preview notation from TSV911 DBV (SOT-23) package Go
Added DCK (SC70) package information to Device Comparison TableGo
Deleted TSV911 DBV (SOT-23) package preview notation from Pin Configuration and Functions sectionGo
Added TSV911 DCK (SC70) package drawing and pin functions Go
Added TSV911 DBV and DCK package thermal informationGo

Changes from A Revision (October 2017) to B Revision

Changed 「製品情報」表で、TSV914 14ピンTSSOPパッケージをプレビューから量産データにGo
Deleted 「製品情報」表の8ピンWSONパッケージからパッケージのプレビュー版の注をGo
Deleted package preview note from PW (TSSOP) package from Device Comparison table Go
Deleted package preview note from DSG (WSON) package from Device Comparison tableGo
Deleted package preview note from TSV912 DSG package pinout drawing in Pin Configuration and Functions sectionGo
Added DGK (VSSOP) thermal information to Thermal Information: TSV912 table Go
Deleted package preview note to TSV914 PW (TSSOP) package Thermal Information tableGo
Added PW (TSSOP) package information to Thermal Information: TSV914 tableGo
Changed TSV914 PW (TSSOP) junction-to-ambient thermal resistance from 135.8°C/W to 205.8°C/WGo
Changed TSV914 PW (TSSOP) junction-to-case(top) thermal resistance from 64°C/W to 106.7°C/WGo
Changed TSV914 PW (TSSOP) junction-to-board thermal resistance from 79°C/W to 133.9°C/WGo
Changed TSV914 PW (TSSOP) junction-to-top characterization parameter from 15.7°C/W to 34.4°C/WGo
Changed TSV914 PW (TSSOP) junction-to-board characterization parameter from 78.4°C/W to 132.6°C/WGo

Changes from * Revision (July 2017) to A Revision

Changed 「製品情報」表で、TSV914 14ピンSOICパッケージをプレビューから量産データにGo
Deleted 「製品情報」表からTSV911のSC70、SOT-553、SOICパッケージをGo
Deleted 「製品情報」表からTSV912 VSSOPパッケージをGo
Deleted TSV911 SC70 and SOIC packages from pinout drawings and Pin Functions tableGo
Deleted TSV912 DGK and DGS packages from pinout images Pin Functions tableGo
Deleted package preview note from TSV914 pinout drawing and Pin Functions table Go
Added TSV914 Thermal Information table Go
Added 2017 copyright notice to Figure 35Go

5 Device Comparison Table

DEVICE	NO. OF CHANNELS	PACKAGE LEADS
DEVICE	NO. OF CHANNELS	DBV	DCK	D	DSG	PW	DDF
TSV911	1	5	5	—	—	—	—
TSV912	2	—	—	8	8	—	8
TSV914	4	—	—	14	—	14	—

6 Pin Configuration and Functions

TSV911 DBV Package

5-Pin SOT-23

Top View

TSV911 TSV912 TSV914 po_sot23-5_bos406.gif

TSV911 DCK Package

5-Pin SC70

Top View

Pin Functions: TSV911

PIN			I/O	DESCRIPTION
NAME	NO.
NAME	DBV (SOT-23)	DCK (SC70)
–IN	4	3	I	Inverting input
+IN	3	1	I	Noninverting input
OUT	1	4	O	Output
V–	2	2	—	Negative (lowest) supply or ground (for single-supply operation)
V+	5	5	—	Positive (highest) supply

TSV912 D, DGK, DDF Packages

8-Pin SOIC, VSSOP

Top View

TSV911 TSV912 TSV914 po_so_msop_bos406.gif

TSV912 DSG Package

8-Pin WSON With Exposed Thermal Pad

Top View

TSV911 TSV912 TSV914 po_drb_dfn-8_bos563.gif

1. Connect exposed thermal pad to V–. See Packages with an Exposed Thermal Pad section for more information.

Pin Functions: TSV912

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
–IN A	2	I	Inverting input, channel A
+IN A	3	I	Noninverting input, channel A
–IN B	6	I	Inverting input, channel B
+IN B	5	I	Noninverting input, channel B
OUT A	1	O	Output, channel A
OUT B	7	O	Output, channel B
V–	4	—	Negative (lowest) supply or ground (for single-supply operation)
V+	8	—	Positive (highest) supply

TSV914 D, PW Packages

14-Pin SOIC, TSSOP

Top View

TSV911 TSV912 TSV914 po_pw_tssop-14_bos563.gif

Pin Functions: TSV914

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
–IN A	2	I	Inverting input, channel A
+IN A	3	I	Noninverting input, channel A
–IN B	6	I	Inverting input, channel B
+IN B	5	I	Noninverting input, channel B
–IN C	9	I	Inverting input, channel C
+IN C	10	I	Noninverting input, channel C
–IN D	13	I	Inverting input, channel D
+IN D	12	I	Noninverting input, channel D
OUT A	1	O	Output, channel A
OUT B	7	O	Output, channel B
OUT C	8	O	Output, channel C
OUT D	14	O	Output, channel D
V–	11	—	Negative (lowest) supply or ground (for single-supply operation)
V+	4	—	Positive (highest) supply

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
Supply voltage				6	V
Signal input pins	Voltage⁽²⁾	Common-mode	(V–) – 0.5	(V+) + 0.5	V
	Voltage⁽²⁾	Differential		(V+) – (V–) + 0.2	V
	Current⁽²⁾		–10	10	mA
Output short-circuit⁽³⁾			Continuous		mA
Specified, T_A			–40	125	°C
Junction, T_J				150	°C
Storage, T_stg			–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply rails to 10 mA or less.

(3) Short-circuit to ground, one amplifier per package.

7.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted)

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_S	Supply voltage	2.5	5.5	V
	Specified temperature	–40	125	°C

7.4 Thermal Information: TSV911

THERMAL METRIC⁽¹⁾		TSV911		UNIT
		DBV (SOT-23)	DCK (SC70)
		5 PINS	5 PINS
R_θJA	Junction-to-ambient thermal resistance	221.7	263.3	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	144.7	75.5	°C/W
R_θJB	Junction-to-board thermal resistance	49.7	51.0	°C/W
ψ_JT	Junction-to-top characterization parameter	26.1	1.0	°C/W
ψ_JB	Junction-to-board characterization parameter	49.0	50.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Thermal Information: TSV912

THERMAL METRIC⁽¹⁾		TSV912				UNIT
		D (SOIC)	DGK (VSSOP)	DSG (WSON)	DDF (SOT-23)
		8 PINS	8 PINS	8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	157.6	201.2	94.4	184.4	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	104.6	85.7	116.5	112.8	°C/W
R_θJB	Junction-to-board thermal resistance	99.7	122.9	61.3	99.9	°C/W
ψ_JT	Junction-to-top characterization parameter	55.6	21.2	13	18.7	°C/W
ψ_JB	Junction-to-board characterization parameter	99.2	121.4	61.7	99.3	°C/W
R_θJC(bot)	Junction-to-case(bottom) thermal resistance	N/A	N/A	34.4	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.6 Thermal Information: TSV914

THERMAL METRIC⁽¹⁾		TSV914		UNIT
		D (SOIC)	PW (TSSOP)
		14 PINS	14 PINS
R_θJA	Junction-to-ambient thermal resistance	106.9	205.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	69	106.7	°C/W
R_θJB	Junction-to-board thermal resistance	63	133.9	°C/W
ψ_JT	Junction-to-top characterization parameter	25.9	34.4	°C/W
ψ_JB	Junction-to-board characterization parameter	62.7	132.6	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.7 Electrical Characteristics: V_S (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V

at T_A = 25°C, R_L = 10 kΩ connected to V_S / 2, V_CM = V_S / 2, and V_OUT = V_S / 2 (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OFFSET VOLTAGE
V_OS	Input offset voltage	V_S = 5 V		±0.3	±1.5	mV
V_OS	Input offset voltage	V_S = 5 V T_A = –40°C to 125°C			±3	mV
dV_OS/dT	Drift	V_S = 5 V T_A = –40°C to 125°C		±0.5		µV/°C
PSRR	Power-supply rejection ratio	V_S = 2.5 V – 5.5 V, V_CM = (V–)		±7		µV/V
	Channel separation, DC	At DC		100		dB
INPUT VOLTAGE RANGE
V_CM	Common-mode voltage range	V_S = 2.5 V to 5.5 V	(V–) – 0.1		(V+) + 0.1	V
CMRR	Common-mode rejection ratio	V_S = 5.5 V (V–) – 0.1 V < V_CM < (V+) – 1.4 V T_A = –40°C to 125°C	80	103		dB
		V_S = 5.5 V, V_CM = –0.1 V to 5.6 V T_A = –40°C to 125°C	57	87
		V_S = 2.5 V, (V–) – 0.1 V < V_CM < (V+) – 1.4 V T_A = –40°C to 125°C		88
		V_S = 2.5 V, V_CM = –0.1 V to 1.9 V T_A = –40°C to 125°C		81
INPUT BIAS CURRENT
I_B	Input bias current			±1		pA
I_OS	Input offset current			±0.05		pA
NOISE
E_n	Input voltage noise (peak-to-peak)	V_S = 5 V, f = 0.1 Hz to 10 Hz		4.77		µV_PP
e_n	Input voltage noise density	V_S = 5 V, f = 10 kHz		12		nV/√Hz
e_n	Input voltage noise density	V_S = 5 V, f = 1 kHz		18		nV/√Hz
i_n	Input current noise density	f = 1 kHz		10		fA/√Hz
INPUT CAPACITANCE
C_ID	Differential			2		pF
C_IC	Common-mode			4		pF
OPEN-LOOP GAIN
A_OL	Open-loop voltage gain	V_S = 2.5 V, (V–) + 0.04 V < V_O < (V+) – 0.04 V R_L = 10 kΩ		100		dB
		V_S = 5.5 V, (V–) + 0.05 V < V_O < (V+) – 0.05 V R_L = 10 kΩ	104	130
		V_S = 2.5 V, (V–) + 0.06 V < V_O < (V+) – 0.06 V R_L = 2 kΩ		100
		V_S = 5.5 V, (V–) + 0.15 V < V_O < (V+) – 0.15 V R_L = 2 kΩ		130
FREQUENCY RESPONSE
GBP	Gain bandwidth product	V_S = 5 V, G = 1		8		MHz
φ_m	Phase margin	V_S = 5 V, G = 1		55		°
SR	Slew rate	V_S = 5 V, G = 1 R_L = 2 kΩ C_L = 100 pF		4.5		V/µs
t_S	Settling time	To 0.1%, V_S = 5 V, 2-V step , G = 1 C_L = 100 pF		0.5		µs
t_S	Settling time	To 0.01%, V_S = 5 V, 2-V step , G = 1 C_L = 100 pF		1		µs
t_OR	Overload recovery time	V_S = 5 V, V_IN × gain > V_S		0.2		µs
THD + N	Total harmonic distortion + noise⁽¹⁾	V_S = 5 V, V_O = 1 V_RMS, G = 1, f = 1 kHz		0.0008%
OUTPUT
V_O	Voltage output swing from supply rails	V_S = 5.5 V, R_L = 10 kΩ			15	mV
V_O	Voltage output swing from supply rails	V_S = 5.5 V, R_L = 2 kΩ			50	mV
I_SC	Short-circuit current	V_S = 5 V		±50		mA
Z_O	Open-loop output impedance	V_S = 5 V, f = 10 MHz		100		Ω
POWER SUPPLY
I_Q	Quiescent current per amplifier	V_S = 5.5 V, I_O = 0 mA		550	750	µA
I_Q	Quiescent current per amplifier	V_S = 5.5 V, I_O = 0 mA T_A = –40°C to 125°C			1100	µA

(1) Third-order filter; bandwidth = 80 kHz at –3 dB.

7.8 Typical Characteristics

at T_A = 25°C, V_S = 5.5 V, R_L = 10 kΩ connected to V_S / 2, V_CM = V_S / 2, and V_OUT = V_S / 2 (unless otherwise noted)

Figure 1. Offset Voltage Production Distribution

Figure 3. Offset Voltage vs Temperature

V_S= 2.5 V to 5.5 V

Figure 5. Offset Voltage vs Power Supply

Figure 7. Closed-Loop Gain vs Frequency

V+ = 2.75 V, V– = –2.75 V

Figure 9. Output Voltage Swing vs Output Current

V_S = 5.5 V	V_CM = (V–) – 0.1 V to (V+) + 0.1 V	R_L= 10 kΩ
T_A= –40°C to 125°C

Figure 11. CMRR vs Temperature

	V_S = 2.5 V to 5.5 V

Figure 13. PSRR vs Temperature

Figure 15. Input Voltage Noise Spectral Density vs Frequency

V_S = 5.5 V	V_CM = 2.5 V	R_L = 2 kΩ
G = 1	BW = 80 kHz	f = 1 kHz

Figure 17. THD + N vs Amplitude

Figure 19. Quiescent Current vs Supply Voltage

Figure 21. Open-Loop Output Impedance vs Frequency

V+ = 2.75 V	V– = –2.75 V	R_L = 10 kΩ
G = –1 V/V	V_OUT step = 100 mV_p-p

Figure 23. Small-Signal Overshoot vs Load Capacitance

V+ = 2.75 V, V– = –2.75 V, G = –10 V/V

Figure 25. Overload Recovery

V+ = 2.75 V	V– = –2.75 V	C_L = 100 pF
G = 1 V/V

Figure 27. Large-Signal Step Response

P_RF = –10 dBm

Figure 29. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency

	V_S = 5.5 V

Figure 31. Phase Margin vs Capacitive Load

Figure 33. Large Signal Settling Time (Positive)

T_A = –40°C to 125°C

Figure 2. Offset Voltage Drift Distribution

V+ = 2.75 V, V– = –2.75 V

Figure 4. Offset Voltage vs Common-Mode Voltage

C_L = 10 pF

Figure 6. Open-Loop Gain and Phase vs Frequency

Figure 8. Input Bias Current vs Temperature

Figure 10. CMRR and PSRR vs Frequency
(Referred to Input)

V_S = 5.5 V	V_CM = (V–) –0.1 V to (V+) –1.4 V	R_L= 10 kΩ
T_A= –40°C to 125°C

Figure 12. CMRR vs Temperature

V_S = 2.5 V to 5.5 V

Figure 14. 0.1-Hz to 10-Hz Input Voltage Noise

V_S = 5.5 V	V_CM = 2.5 V	R_L = 2 kΩ
G = 1	V_OUT = 0.5 V_RMS	BW = 80 kHz

Figure 16. THD + N vs Frequency

V_S = 5.5 V	V_CM = 2.5 V	R_L = 2 kΩ
G = –1	BW = 80 kHz	f = 1 kHz

Figure 18. THD + N vs Amplitude

Figure 20. Quiescent Current vs Temperature

V+ = 2.75 V	V– = –2.75 V	G = 1 V/V
R_L = 10 kΩ	V_OUT step = 100 mV_p-p

Figure 22. Small-Signal Overshoot vs Load Capacitance

V+ = 2.75 V, V– = –2.75 V

Figure 24. No Phase Reversal

V+ = 2.75 V, V– = –2.75 V, G = 1 V/V

Figure 26. Small-Signal Step Response

Figure 28. Short-Circuit Current vs Temperature

V+ = 2.75 V, V– = –2.75 V

Figure 30. Channel Separation vs Frequency

	V_S = 5.5 V

Figure 32. Open Loop Voltage Gain vs Output Voltage

Figure 34. Large Signal Settling Time (Negative)

8 Detailed Description

8.1 Overview

The TSV91x series is a family of low-power, rail-to-rail input and output op amps. These devices operate from 2.5 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input common-mode voltage range includes both rails and allows the TSV91x series to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications and are designed for driving sampling analog-to-digital converters (ADCs).