JAJSKH6A April   2022  – May 2024 TUSB1004

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4.   概要
  5. 3 Pin Configuration and Functions
  6. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Power Supply Characteristics
    6. 4.6  Control I/O DC Electrical Characteristics
    7. 4.7  USB Electrical Characteristics
    8. 4.8  Timing Requirements
    9. 4.9  Switching Characteristics
    10. 4.10 Typical Characteristics
  7. 5 Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Inputs
      2. 6.3.2 USB Receiver Linear Equalization
        1. 6.3.2.1 Linear EQ Configuration
        2. 6.3.2.2 Full Adaptive Equalization
        3. 6.3.2.3 Fast Adaptive Equalization
      3. 6.3.3 USB Transmitter
        1. 6.3.3.1 Linearity VOD
        2. 6.3.3.2 Limited VOD
        3. 6.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 6.3.4 USB 3.1 x2 Description
      5. 6.3.5 USB Polarity Inversion
      6. 6.3.6 Receiver Detect Control
    4. 6.4 Device Functional Modes
      1. 6.4.1 MODE Pin
      2. 6.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 6.4.3 USB 3.2 Power States
      4. 6.4.4 Disabling U1 and U2
    5. 6.5 Programming
      1. 6.5.1 Pseudocode Examples
        1. 6.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 6.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 6.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 6.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 6.5.1.5 Full AEQ with Linear Redriver Mode
        6. 6.5.1.6 Full AEQ with Limited Redriver Mode
      2. 6.5.2 TUSB1004 I2C Address Options
      3. 6.5.3 TUSB1004 I2C Target Behavior
    6. 6.6 Register Map
      1. 6.6.1 TUSB1004 Registers
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 USB SSTX1/2 Receiver Configuration
        2. 7.2.2.2 USB CRX1/2 Receiver Configuration
          1. 7.2.2.2.1 Fixed Equalization
          2. 7.2.2.2.2 Full Adaptive Equalization
          3. 7.2.2.2.3 Fast Adaptive Equalization
        3. 7.2.2.3 ESD Protection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Pin Configuration and Functions

TUSB1004 TUSB1004 RNQ Package, 40-Pin WQFN (Top View) Figure 3-1 TUSB1004 RNQ Package, 40-Pin WQFN (Top View)
Table 3-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
VCC1P3.3 V supply
SSEQ1/A124-level I
(PU/PD)		In I2C mode, this pin along with A0 pin selects the 7-bit I2C target address (refer to Table 6-7). In pin-strap mode, this pin along with SSEQ0 selects the receiver EQ for SSTX1 and/or SSTX2 (refer to Table 6-3).
EQCFG34-level I
(PU/PD)		In pin-strap mode, this controls how CEQ[1:0] pins and SSEQ[1:0] are used. Refer to Rx EQ Configuration in Pin-Strap Mode for details. In I2C mode, this pin is for TI internal test and must be left floating for normal operation.
SLP_S0#4I
(PU)		SLP_S0#. This pin will control whether or not Rx.Detect function is enabled. If this pin is low and device is in Disconnect state, Rx termination will be disabled. If this pin is low and device is U2/U3 state, Rx termination will be enabled.
1: Rx.Detect Enabled.
0: Rx.Detect Disabled.
NC5No internal connection.
VCC6P3.3 V supply
TESTOUT17OFor internal TI test only. For normal operation this pin should be left unconnected.
TESTOUT28OFor internal TI test only. For normal operation this pin should be left unconnected.
SSTX2p 9 I Differential positive input for USB port 2. Should be connected to USB 3.2 Host transmit port through an external 220 nF AC-coupling capacitor.
SSTX2n 10 I Differential positive input for USB port 2. Should be connected to USB 3.2 Host transmit port through an external 220 nF AC-coupling capacitor.
NC11No internal connection.
SSRX2p 12 O Differential positive output for USB port 2. Should be connected to USB 3.2 Host receiver port through an external 220 nF AC-coupling capacitor.
SSRX2n 13 O Differential negative output for USB port 2. Should be connected to USB 3.2 Host receiver port through an external 220 nF AC-coupling capacitor.
VIO_SEL144-level I
(PU/PD)		Selects the input thresholds for I2C (SDA and SCL).
"0": I2C 3.3 V
"R": I2C 1.8 V
"F": I2C 3.3 V.
"1": I2C 1.8 V.
SSTX1p 15 I Differential positive input for USB port 1. Should be connected to USB 3.2 Host transmit port through an external 220 nF AC-coupling capacitor.
SSTX1n 16 I Differential negative input for USB port 1. Should be connected to USB 3.2 Host transmit port through an external 220 nF AC-coupling capacitor.
MODE174-level I
(PU/PD)		This pin selects whether device is in I2C mode or pin-strap mode. Refer to Table 6-4 for details.
SSRX1p 18 O Differential positive output for USB port 1. Should be connected to USB 3.2 Host receiver port through an external 220 nF AC-coupling capacitor.
SSRX1n 19 O Differential negative output for USB port 1. Should be connected to USB 3.2 Host receiver port through an external 220 nF AC-coupling capacitor.
VCC20P3.3 V supply
TEST2/SCL 21 I In I2C mode, this pin functions as I2C clock.
In pin-strap mode, this pin is used for TI internal test and should be pulldown or tied to GND for normal operation.
AEQENZ/SDA22I/OIn I2C mode, this pin functions as I2C data. In pin-strap mode, this pin controls whether or not AEQ is enabled.
0: AEQ enabled
1: AEQ disabled
AEQCFG234-level I
(PU/PD)

In pin-strap mode, this pin controls the FULLAEQ_UPPER_EQ limit. In I2C mode, this function is controlled by the FULLAEQ_UPPER_EQ register.
"0": FULLAEQ_UPPER_EQ = Ah
"R": FULLAEQ_UPPER_EQ = Fh
"F": FULLAEQ_UPPER_EQ = 8h
"1": FULLAEQ_UPPER_EQ = Ch

NC24No internal connection
NC25No internal connection
EN 26 I
(PU)		 When low, the differential receiver's termination will be disabled and differential drivers will be disabled. On rising edge of EN, device will sample four-level inputs and function based on the sampled state of the pins. This pin has a internal 500k pullup to VCC. Please note this pin will also reset internal configuration registers.
TEST1 27 I TI Test1. Under normal operations this pin shall be connected directly or pulled up to VCC.
VCC28P3.3 V supply
CEQ1294-level I
(PU/PD)		In pin-strap mode, this pin along with CEQ0 selects the receiver EQ for CRX1 and/or CRX2 (Refer to Table 6-2).
CRX1n 30 I Differential negative input for USB port 1. Should be connected to SSRXn pin of USB connector. Connection can be DC-coupled to USB connector. Optionally, connection can be through an external 330 nF AC-coupling capacitor.
CRX1p 31 I Differential positive input for USB port 1. Should be connected to SSRXp pin of USB connector. Connection can be DC-coupled to USB connector. Optionally, connection can be through an external 330 nF AC-coupling capacitor.
NC32No internal connection.
CTX1n 33 O Differential negative output for USB port 1. Should be connected to SSTXn pin of USB connector through an external 220 nF AC-coupling capacitor.
CTX1p 34 O Differential positive output for USB port 1. Should be connected to SSTXp pin of USB connector through an external 220 nF AC-coupling capacitor.
SSEQ0/A0354-level I
(PU/PD)		In I2C mode, this pin along with A1 pin selects the 7-bit I2C target address (refer to Table 6-7). In pin-strap mode, this pin along with SSEQ1 selects the receiver EQ for SSTX1 and/or SSTX2 (refer to Table 6-3).
CRX2n 36 I Differential negative input for USB port 2. Should be connected to SSRXn pin of USB connector. Connection can be DC-coupled to USB connector. Optionally, connection can be through an external 330 nF AC-coupling capacitor.
CRX2p 37 I Differential positive input for USB port 2. Should be connected to SSRXp pin of USB connector. Connection can be DC-coupled to USB connector. Optionally, connection can be through an external 330 nF AC-coupling capacitor.
CEQ0384-level I
(PU/PD)		In pin-strap mode, this pin along with CEQ1 selects the receiver EQ for CRX1 and/or CRX2 (Refer to Table 6-2).
CTX2n 39 O Differential negative output for USB port 2. Should be connected to SSTXn pin of USB connector through an external 220 nF AC-coupling capacitor.
CTX2p 40 O Differential positive output for USB port 2. Should be connected to SSTXp pin of USB connector through an external 220 nF AC-coupling capacitor.
Thermal PadGThermal pad. Connect to a solid ground plane.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, PD = Internal Pulldown, PU = Internal Pullup.