JAJSNA3 September   2024 TUSB1064-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 USB3 Modes
      6. 7.4.6 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB1064-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
        2. 8.2.2.2 Support for DisplayPort UFP_D Pin Assignment E
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
    3. 9.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
    4. 9.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
    5. 9.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
    6. 9.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
    7. 9.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
    8. 9.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.4 Linear EQ Configuration

Each of the TUSB1064-Q1 receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 7-7 details the gain value for each available combination when TUSB1064-Q1 is in GPIO mode. These same options are also available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and SSEQ_SEL. Each of the 4-bit EQ configuration registers is mapped to the configuration pins as follows: x_SEL = {x1[1:0],x0[1:0]} where xn[1:0] are the EQ configuration pins with pin levels mapped to 2-bit values as: 0 = 00, R = 01, F = 10, 1 = 11.

Table 7-7 TUSB1064-Q1 Receiver Equalization GPIO Control
EQUALIZATION SETTING #USB3.2 UPSTREAM FACING PORTSUSB 3.2 DOWNSTREAM FACING PORTALL DISPLAYPORT LANES
EQ1 PIN LEVELEQ0 PIN LEVELEQ GAIN AT 5GHz (dB)SSEQ1 PIN LEVELSSEQ0 PIN LEVELEQ GAIN AT 5GHz (dB)DPEQ1 PIN LEVELDPEQ0 PIN LEVELEQ GAIN AT 4.05GHz (dB)
0 0 0 0.4 0 0 -2.4 0 0 1.0
1 0 R 2.6 0 R -0.2 0 R 3.0
2 0 F 4.2 0 F 1.3 0 F 4.4
3 0 1 5.7 0 1 2.8 0 1 5.8
4 R 0 6.7 R 0 3.8 R 0 6.8
5 R R 7.9 R R 4.9 R R 8.0
6 R F 8.7 R F 5.8 R F 8.8
7 R 1 9.5 R 1 6.6 R 1 9.6
8 F 0 10.2 F 0 7.3 F 0 10.4
9 F R 10.9 F R 7.9 F R 11.0
10 F F 11.4 F F 8.4 F F 11.6
11 F 1 11.9 F 1 8.9 F 1 12.1
12 1 0 12.2 1 0 9.3 1 0 12.5
13 1 R 12.6 1 R 9.7 1 R 13.0
14 1 F 12.9 1 F 10.0 1 F 13.4
15 1 1 13.3 1 1 10.5 1 1 13.7