JAJSKH4A April   2022  – May 2024 TUSB1104

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4.   概要
  5. 3 Pin Configuration and Functions
  6. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Power Supply Characteristics
    6. 4.6  Control I/O DC Electrical Characteristics
    7. 4.7  USB Electrical Characteristics
    8. 4.8  Timing Requirements
    9. 4.9  Switching Characteristics
    10. 4.10 Typical Characteristics
  7. 5 Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Inputs
      2. 6.3.2 USB Receiver Linear Equalization
        1. 6.3.2.1 Linear EQ Configuration
        2. 6.3.2.2 Full Adaptive Equalization
        3. 6.3.2.3 Fast Adaptive Equalization
      3. 6.3.3 USB Transmitter
        1. 6.3.3.1 Linearity VOD
        2. 6.3.3.2 Limited VOD
        3. 6.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 6.3.4 USB 3.2 x2 Description
      5. 6.3.5 USB Polarity Inversion
      6. 6.3.6 Receiver Detect Control
    4. 6.4 Device Functional Modes
      1. 6.4.1 MODE Pin
      2. 6.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 6.4.3 USB 3.2 Power States
      4. 6.4.4 Disabling U1 and U2
    5. 6.5 Programming
      1. 6.5.1 Pseudocode Examples
        1. 6.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 6.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 6.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 6.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 6.5.1.5 Full AEQ with Linear Redriver Mode
        6. 6.5.1.6 Full AEQ with Limited Redriver Mode
      2. 6.5.2 TUSB1104 I2C Address Options
      3. 6.5.3 TUSB1104 I2C Target Behavior
    6. 6.6 Register Map
      1. 6.6.1 Device Registers
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 USB SSTX1/2 Receiver Configuration
        2. 7.2.2.2 USB CRX1/2 Receiver Configuration
          1. 7.2.2.2.1 Fixed Equalization
          2. 7.2.2.2.2 Full Adaptive Equalization
          3. 7.2.2.2.3 Fast Adaptive Equalization
        3. 7.2.2.3 ESD Protection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.4 USB 3.2 x2 Description

The TUSB1104 configured for USB 3.2 x2 mode will determine if the link is operating in USB 3.2 x2 or in USB 3.1 x1. If the link is USB 3.2 x2, then TUSB1104 will operate with one port operating as a USB 3.2 x1 port and the remaining port following the lead of the other port. The port functioning as a USB 3.1 x1 port is called the config lane. The determination of the config lane is based solely on the Type-C orientation. For normal orientation (FLIP = L), Port 1 is the config lane. For the flipped orientation (FLIP = H), Port 2 is the config lane.

In USB 3.2 x2 the config lane will operate as a standard USB 3.2 x1 port. While in all USB low power states (Disconnect, U1, U2, and U3), the non-config lane will be disabled in order to conserve power. Entry to and exit from these low power states is determined solely by the config lane. If the config lane detects an exit from a low power state, then the non-config will be enabled.

Table 6-4 Config Lane Selection
FLIP pin or FLIP_SEL register CONFIG LANE NON-CONFIG LANE
0 CRX1 -> SSRX1 CRX2 -> SSRX2
SSTX1 -> CTX1 SSTX2 -> CTX2
1 CRX2 -> SSRX2 CRX1 -> SSRX1
SSTX2 -> CTX2 SSTX1 -> CTX1