SLLSE80B March   2011  – June 2015 TUSB1211

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagram
      1. 3.1.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Power Consumption Summary
    5. 4.5  Electrical Characteristics - Analog Output Pins
    6. 4.6  Electrical Characteristics - Analog Input Pins
    7. 4.7  Digital I/O Electrical Characteristics - Non-ULPI Pins
    8. 4.8  Digital I/O Electrical Characteristics - Non-ULPI Pins
    9. 4.9  Electrical Characteristics - REFCLK
    10. 4.10 Electrical Characteristics - CLOCK Input
    11. 4.11 Electrical Characteristics - REFCLK
    12. 4.12 Electrical Characteristics - CK32K Clock Generator
    13. 4.13 Thermal Characteristics
    14. 4.14 REG3V3 Internal LDO Regulator Characteristics
    15. 4.15 REG1V8 Internal LDO Regulator Characteristics
    16. 4.16 REG1V5 Internal LDO Regulator Characteristics
    17. 4.17 Timers and Debounce
    18. 4.18 OTG VBUS Electrical
    19. 4.19 LS/FS Single-Ended Receivers
    20. 4.20 LS/FS Differential Receiver
    21. 4.21 LS Transmitter
    22. 4.22 FS Transmitter
    23. 4.23 HS Transmitter
    24. 4.24 Pullup and Pulldown Resistors
    25. 4.25 Autoresume Watchdog Timer
    26. 4.26 UART Transceiver
    27. 4.27 OTG ID Electrical
    28. 4.28 Electrical Specs - Charger Detection Currents
    29. 4.29 Electrical Specs - Resistance
    30. 4.30 Electrical Specs - Capacitance
    31. 4.31 Charger Detection Debounce and Wait Timing
    32. 4.32 ULPI Interface
      1. 4.32.1 ULPI Interface Timing
    33. 4.33 Power-On Timing Diagrams
      1. 4.33.1 Standard Power-up Timing
      2. 4.33.2 Hardware Charger Detection Power-Up Timing
    34. 4.34 Clock System
      1. 4.34.1 USB PLL Reference Clock
        1. 4.34.1.1 ULPI Input Clock Configuration
        2. 4.34.1.2 ULPI Output Clock Configuration
    35. 4.35 Clock System
      1. 4.35.1 Internal Clock Generator (32 kHz)
    36. 4.36 Power Management
      1. 4.36.1 Power Provider
    37. 4.37 Power Provider
      1. 4.37.1 REG3V3 Regulator
      2. 4.37.2 REG1V8 Regulator
      3. 4.37.3 REG1V5 Regulator
    38. 4.38 Power Control
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  USB On-The-Go (OTG) Feature
      2. 5.3.2  VBUS Detection Status Bits vs VBUS Comparators
      3. 5.3.3  USB Transceiver (PHY)
        1. 5.3.3.1 PHY Overview
      4. 5.3.4  LS/FS Single-Ended Receivers
      5. 5.3.5  LS/FS Differential Receiver
      6. 5.3.6  LS/FS Transmitter
      7. 5.3.7  HS Differential Receiver
      8. 5.3.8  HS Differential Transmitter
      9. 5.3.9  Autoresume
      10. 5.3.10 UART Transceiver
      11. 5.3.11 USB On-The-Go (OTG)
        1. 5.3.11.1 ID Detection Status Bits vs ID Comparators
      12. 5.3.12 USB Battery Charger Detection and ACA
      13. 5.3.13 USB Battery Charger Detection Modes
      14. 5.3.14 Accessory Charger Adapter (ACA) Detection
    4. 5.4 Register Maps
      1. 5.4.1  VENDOR_ID_LO
      2. 5.4.2  VENDOR_ID_HI
      3. 5.4.3  PRODUCT_ID_LO
      4. 5.4.4  PRODUCT_ID_HI
      5. 5.4.5  FUNC_CTRL
      6. 5.4.6  FUNC_CTRL_SET
      7. 5.4.7  FUNC_CTRL_CLR
      8. 5.4.8  IFC_CTRL
      9. 5.4.9  IFC_CTRL_SET
      10. 5.4.10 IFC_CTRL_CLR
      11. 5.4.11 OTG_CTRL
      12. 5.4.12 OTG_CTRL_SET
      13. 5.4.13 OTG_CTRL_CLR
      14. 5.4.14 USB_INT_EN_RISE
      15. 5.4.15 USB_INT_EN_RISE_SET
      16. 5.4.16 USB_INT_EN_RISE_CLR
      17. 5.4.17 USB_INT_EN_FALL
      18. 5.4.18 USB_INT_EN_FALL_SET
      19. 5.4.19 USB_INT_EN_FALL_CLR
      20. 5.4.20 USB_INT_STS
      21. 5.4.21 USB_INT_LATCH
      22. 5.4.22 DEBUG
      23. 5.4.23 SCRATCH_REG
      24. 5.4.24 SCRATCH_REG_SET
      25. 5.4.25 SCRATCH_REG_CLR
      26. 5.4.26 POWER_CONTROL
      27. 5.4.27 POWER_CONTROL_SET
      28. 5.4.28 POWER_CONTROL_CLR
      29. 5.4.29 VENDOR_SPECIFIC1
      30. 5.4.30 VENDOR_SPECIFIC1_SET
      31. 5.4.31 VENDOR_SPECIFIC1_CLR
      32. 5.4.32 VENDOR_SPECIFIC2_STS
      33. 5.4.33 VENDOR_SPECIFIC2_LATCH
      34. 5.4.34 VENDOR_SPECIFIC3
      35. 5.4.35 VENDOR_SPECIFIC3_SET
      36. 5.4.36 VENDOR_SPECIFIC3_CLR
      37. 5.4.37 VENDOR_SPECIFIC4
      38. 5.4.38 VENDOR_SPECIFIC4_SET
      39. 5.4.39 VENDOR_SPECIFIC4_CLR
      40. 5.4.40 VENDOR_SPECIFIC5
      41. 5.4.41 VENDOR_SPECIFIC5_SET
      42. 5.4.42 VENDOR_SPECIFIC5_CLR
      43. 5.4.43 VENDOR_SPECIFIC6
      44. 5.4.44 VENDOR_SPECIFIC6_SET
      45. 5.4.45 VENDOR_SPECIFIC6_CLR
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Unused Pins Connection
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Ground
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
      2. 7.1.2 Community Resources
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Application, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

6.1 Application Information

Figure 6-1 shows the suggested application diagram (host or OTG, ULPI output-clock mode).

The TUSB1211 is a USB2.0 transceiver chip, designed to interface with a USB controller through a ULPI interface. The device supports all USB2.0 data rates (high-speed, full-speed, and low-speed) and it is compliant to both host and peripheral (OTG) modes. Use Section 6.2.1 and Section 6.2.2 to select the wished operation mode. This section presents a simplified discussion of the design process.

6.2 Typical Application

TUSB1211 appdiag_llse44.gif
A. Optional: SOF (open if unused); RESET_N (tie to VDDIO if unused)
B. Link controls chip select through CS pin with CS_N at GND. Alternatively, Link may control CS_N pin with CS pin tied to VDDIO.
C. CHRG_DET is active-low (tie CHRG_POL to VBAT for CHRG_DET active high).
D. Dead battery charger detection is enabled (tie CHRG_EN_N to VBAT to disable).
E. CFG tied to VDDIO for 26 MHz input at REFCLK (tie to GND for 19.2 MHz).
Figure 6-1 USB-OTG With ULPI Output Clock

6.2.1 Design Requirements

Table 6-1 Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VBAT 3.3 V
VDDIO 1.8 V
VBUS 5 V
USB Support HS, FS, LS
USB Battery Charger Detection Yes
USB On the Go (OTG) Yes
Clock sources 26 MHz or 19.2 MHz oscillator

6.2.2 Detailed Design Procedure

Connect the TUSB12111 device as is shown in the suggested application diagram, Figure 6-1. Follow the Board Guidelines of the Application Report, TUSB121x USB2.0 Board Guidelines (SWCA124)

Table 6-2 External Components

FUNCTION COMPONENT REFERENCE VALUE NOTE
VDDIO Capacitor CVDDIO.IN 100 nF Suggested value, application dependent
REG3V3 Capacitor CREG3V3 2.2 µF (recommended)

Range: [0.45 μF : 6.5 μF]

ESR = [0 : 600 mΩ] for f > 10 kHz
REG1V5 Capacitor CREG1V5 2.2 µF (recommended)

Range: [0.45 μF : 6.5 μF]

ESR = [0 : 600 mΩ] for f > 10 kHz
VBAT Capacitor CBYP 2.2 µF (recommended)

Range: [0.45 μF : 6.5 μF]

ESR = [0 : 600 mΩ] for f > 10 kHz
VBUS Capacitor CVBUS 4.7 µF (recommended) Place close to USB connector

Table 6-3 VBUS Capacitors

FUNCTION COMPONENT REFERENCE VALUE NOTE
VBUS – HOST Capacitor CVBUS > 120 μF
VBUS – DEVICE Capacitor CVBUS 4.7 μF Range: 1.0 μF to 10.0 μF
VBUS – OTG Capacitor CVBUS 4.7 μF Range: 1.0 μF to 6.5 μF

6.2.2.1 Unused Pins Connection

  • CHRG_DET Output. Leave floating if unused.
  • CHRG_POL Input. Tie to GND to make CHRG_DET pin active low if unused.
  • CHRG_EN_N Input. Tie to VBAT to disable dead-battery charger detection if unused.
  • SOF Output. Leave floating if unused.
  • REFCLK Input. If REFCLK is unused, and 60-MHz clock is provided by MODEM (60 MHz should be connected to CLOCK pin in this case) then tie REFCLK to GND.
  • CFG tie to GND if REFCLK is 19.2 MHz, or tie to VDDIO if REFCLK is 26 MHz. Tie to either GND or VDDIO (do not care which) if REFCLK not used (that is, ULPI input clock configuration).

6.2.3 Application Curves

TUSB1211 appcurve1.gif
Figure 6-2 High-Speed Eye Diagram
TUSB1211 appcurve2.gif
Figure 6-3 Full-Speed Eye Diagram

6.3 Layout

6.3.1 Layout Guidelines

  • The VDDIO pins of the TUSB1211 supply 1.8 V (nominal) power to the core of the TUSB1211 device. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
  • The VBAT pin of the TUSB1211 supply 3.3 V (nominal) power rail to the TUSB1211 device. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
  • The VBUS pin of the TUSB1211 supply 5 V (nominal) power rail to the TUSB1211 device. This pin is normally connected to the VBUS pin of the USB connector.
  • All power rails require 0.1-μF decoupling capacitors for stability and noise immunity. The smaller decoupling capacitors should be placed as close to the TUSB1211 device power pins as possible with an optimal grouping of two of differing values per pin.

6.3.1.1 Ground

TI recommends using almost one board ground plane be used in the design. This provides the best image plane for signal traces running above the plane. An earth or chassis ground is implemented only near the USB port connectors on a different plane for EMI and ESD purposes.

6.3.2 Layout Example

TUSB1211 layoutexample.gifFigure 6-4 TUSB1211 Layout

6.4 Power Supply Recommendations

VBUS, VBAT, and VDDIO are needed for power the TUSB1211 device.

The recommended operation is for VBAT to be present before VDDIO. Applying VDDIO before VBAT to the TUSB1211 device is not recommended because a diode from VDDIO to VBAT will be forward-biased when VDDIO is present but VBAT is not present. TUSB121x does not strictly require VBUS to function.