SLLSE80B March   2011  – June 2015 TUSB1211

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagram
      1. 3.1.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Power Consumption Summary
    5. 4.5  Electrical Characteristics - Analog Output Pins
    6. 4.6  Electrical Characteristics - Analog Input Pins
    7. 4.7  Digital I/O Electrical Characteristics - Non-ULPI Pins
    8. 4.8  Digital I/O Electrical Characteristics - Non-ULPI Pins
    9. 4.9  Electrical Characteristics - REFCLK
    10. 4.10 Electrical Characteristics - CLOCK Input
    11. 4.11 Electrical Characteristics - REFCLK
    12. 4.12 Electrical Characteristics - CK32K Clock Generator
    13. 4.13 Thermal Characteristics
    14. 4.14 REG3V3 Internal LDO Regulator Characteristics
    15. 4.15 REG1V8 Internal LDO Regulator Characteristics
    16. 4.16 REG1V5 Internal LDO Regulator Characteristics
    17. 4.17 Timers and Debounce
    18. 4.18 OTG VBUS Electrical
    19. 4.19 LS/FS Single-Ended Receivers
    20. 4.20 LS/FS Differential Receiver
    21. 4.21 LS Transmitter
    22. 4.22 FS Transmitter
    23. 4.23 HS Transmitter
    24. 4.24 Pullup and Pulldown Resistors
    25. 4.25 Autoresume Watchdog Timer
    26. 4.26 UART Transceiver
    27. 4.27 OTG ID Electrical
    28. 4.28 Electrical Specs - Charger Detection Currents
    29. 4.29 Electrical Specs - Resistance
    30. 4.30 Electrical Specs - Capacitance
    31. 4.31 Charger Detection Debounce and Wait Timing
    32. 4.32 ULPI Interface
      1. 4.32.1 ULPI Interface Timing
    33. 4.33 Power-On Timing Diagrams
      1. 4.33.1 Standard Power-up Timing
      2. 4.33.2 Hardware Charger Detection Power-Up Timing
    34. 4.34 Clock System
      1. 4.34.1 USB PLL Reference Clock
        1. 4.34.1.1 ULPI Input Clock Configuration
        2. 4.34.1.2 ULPI Output Clock Configuration
    35. 4.35 Clock System
      1. 4.35.1 Internal Clock Generator (32 kHz)
    36. 4.36 Power Management
      1. 4.36.1 Power Provider
    37. 4.37 Power Provider
      1. 4.37.1 REG3V3 Regulator
      2. 4.37.2 REG1V8 Regulator
      3. 4.37.3 REG1V5 Regulator
    38. 4.38 Power Control
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  USB On-The-Go (OTG) Feature
      2. 5.3.2  VBUS Detection Status Bits vs VBUS Comparators
      3. 5.3.3  USB Transceiver (PHY)
        1. 5.3.3.1 PHY Overview
      4. 5.3.4  LS/FS Single-Ended Receivers
      5. 5.3.5  LS/FS Differential Receiver
      6. 5.3.6  LS/FS Transmitter
      7. 5.3.7  HS Differential Receiver
      8. 5.3.8  HS Differential Transmitter
      9. 5.3.9  Autoresume
      10. 5.3.10 UART Transceiver
      11. 5.3.11 USB On-The-Go (OTG)
        1. 5.3.11.1 ID Detection Status Bits vs ID Comparators
      12. 5.3.12 USB Battery Charger Detection and ACA
      13. 5.3.13 USB Battery Charger Detection Modes
      14. 5.3.14 Accessory Charger Adapter (ACA) Detection
    4. 5.4 Register Maps
      1. 5.4.1  VENDOR_ID_LO
      2. 5.4.2  VENDOR_ID_HI
      3. 5.4.3  PRODUCT_ID_LO
      4. 5.4.4  PRODUCT_ID_HI
      5. 5.4.5  FUNC_CTRL
      6. 5.4.6  FUNC_CTRL_SET
      7. 5.4.7  FUNC_CTRL_CLR
      8. 5.4.8  IFC_CTRL
      9. 5.4.9  IFC_CTRL_SET
      10. 5.4.10 IFC_CTRL_CLR
      11. 5.4.11 OTG_CTRL
      12. 5.4.12 OTG_CTRL_SET
      13. 5.4.13 OTG_CTRL_CLR
      14. 5.4.14 USB_INT_EN_RISE
      15. 5.4.15 USB_INT_EN_RISE_SET
      16. 5.4.16 USB_INT_EN_RISE_CLR
      17. 5.4.17 USB_INT_EN_FALL
      18. 5.4.18 USB_INT_EN_FALL_SET
      19. 5.4.19 USB_INT_EN_FALL_CLR
      20. 5.4.20 USB_INT_STS
      21. 5.4.21 USB_INT_LATCH
      22. 5.4.22 DEBUG
      23. 5.4.23 SCRATCH_REG
      24. 5.4.24 SCRATCH_REG_SET
      25. 5.4.25 SCRATCH_REG_CLR
      26. 5.4.26 POWER_CONTROL
      27. 5.4.27 POWER_CONTROL_SET
      28. 5.4.28 POWER_CONTROL_CLR
      29. 5.4.29 VENDOR_SPECIFIC1
      30. 5.4.30 VENDOR_SPECIFIC1_SET
      31. 5.4.31 VENDOR_SPECIFIC1_CLR
      32. 5.4.32 VENDOR_SPECIFIC2_STS
      33. 5.4.33 VENDOR_SPECIFIC2_LATCH
      34. 5.4.34 VENDOR_SPECIFIC3
      35. 5.4.35 VENDOR_SPECIFIC3_SET
      36. 5.4.36 VENDOR_SPECIFIC3_CLR
      37. 5.4.37 VENDOR_SPECIFIC4
      38. 5.4.38 VENDOR_SPECIFIC4_SET
      39. 5.4.39 VENDOR_SPECIFIC4_CLR
      40. 5.4.40 VENDOR_SPECIFIC5
      41. 5.4.41 VENDOR_SPECIFIC5_SET
      42. 5.4.42 VENDOR_SPECIFIC5_CLR
      43. 5.4.43 VENDOR_SPECIFIC6
      44. 5.4.44 VENDOR_SPECIFIC6_SET
      45. 5.4.45 VENDOR_SPECIFIC6_CLR
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Unused Pins Connection
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Ground
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
      2. 7.1.2 Community Resources
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Pin Configuration and Functions

3.1 Pin Diagram

ZRQ Package
36-Pin TFBGA
Bottom View
TUSB1211 pinmap_llse44.gif
1. NC = Not Connected
2. The size of the device should be 3.5 mm ±0.1 mm by 3.5 mm ±0.1 mm. Height is 1.0 mm typical 1.15 mm max including the solder balls. The pitch of the device is 0.5 mm. Ball width 0.3 mm ±0.05 mm.

3.1.1 Pin Attributes

Pin Functions

NO. PIN(1) NAME A/D(2) TYPE(3) LEVEL(4) DESCRIPTION
1 D5 NXT D O VDDIO ULPI NXT output signal
2 B1 DATA0 D I/O VDDIO ULPI DATA input/output signal synchronized to CLOCK
3 A1 DATA1 D I/O VDDIO ULPI DATA input/output signal synchronized to CLOCK
4 A2 DATA2 D I/O VDDIO ULPI DATA input/output signal synchronized to CLOCK
5 A3 DATA3 D I/O VDDIO ULPI DATA input/output signal synchronized to CLOCK
6 A5 DATA4 D I/O VDDIO ULPI DATA input/output signal synchronized to CLOCK
7 A6 DATA5 D I/O VDDIO ULPI DATA input/output signal synchronized to CLOCK
8 B6 DATA6 D I/O VDDIO ULPI DATA input/output signal synchronized to CLOCK
9 B3 CS D I VDDIO Active-high chip select pin. When low the IC is in power down and ULPI bus is tri-stated. When high (and CS_N pin iTie to VDDIO if unused.s low) normal operation.
10 E6 REG1V5 A POWER VDD15 1.5 V internal LDO output. Connect to external filtering capacitor.
11 C6 DATA7 D I/O VDDIO ULPI DATA input/output signal synchronized to CLOCK
12 B4 CFG D I VDDIO REFCLK clock frequency configuration pin.
Two frequencies are supported: 19.2 MHz when 0, or 26 MHz when 1.
13 D1 DP A I/O VDD33 DP pin of the USB connector
14 C1 DM A I/O VDD33 DM pin of the USB connector
15 E3 REG3V3 A POWER VDD33 3.3 V internal LDO output. Connect to external filtering capacitor.
16 F3 VBAT A POWER VBAT Input supply voltage or battery source. Nominally 3.3 V to 4.5 V
17 F4 VBUS A I/O VBUS VBUS pin of the USB connector
18 D3 ID A I/O VBUS Identification (ID) pin of the USB connector
19 A4 CLOCK D I/O VDDIO ULPI 60-MHz clock on which ULPI data is synchronized. 2 modes are possible:
Input Mode: CLOCK defaults as an input (this is the default clock mode)
Output Mode: When an input clock is detected on REFCLK pin then CLOCK will change to an output
20 C4 RESET_N D I VDDIO Active low chip reset pin. Minimum pulse width 100 µs. When low all digital logic (except 32-kHz logic required for power-up sequencing and charger detection state-machine) including registers are reset to their default values. ULPI bus is in “ULPI Synchronous mode power-up PLL OFF” state as described in Table 5-5. When high normal USB operation.
21 D6 STP D I VDDIO ULPI STP input signal
22 E5 DIR D O VDDIO ULPI DIR output signal
23 B5 VDDIO A I VDDIO External 1.8-V supply input for digital I/Os. Connect to external filtering capacitor.
24 B2 VDDIO A I VDDIO External 1.8-V supply input for digital I/Os. Connect to external filtering capacitor.
25 C5 GND A GROUND GND Ground
26 D2 GND A GROUND GND Ground
27 E4 GND A GROUND GND Ground
28 F5 REFCLK D I VDDIO Reference clock input.
Input reference clock frequency must be indicated by CFG pin.
Two frequencies are supported: 19.2 MHz (when CFG = 0), and 26 MHz (when CFG = 1).
29 F6 SOF D O VDDIO HS USB SOF (Start-of-Frame) output clock. (feature controlled by SOF_EN bit, disabled and output logic low by default.). HS USB SOF packet rate is 8 kHz.
30 C2 NC — — Not connected
31 C3 CS_N D I VDDIO Active-low chip select pin. When high the IC is in power down and ULPI bus is tri-stated. When low (and CS pin is high) normal operation. Tie to GND if unused.
32 E1 CHRG_EN_N D I VBAT Active low input pin used to enable Battery Charging Detection in Dead Battery Charger Detection mode. This pin is ignored in ACTIVE mode. Connect to GND to activate. Connect to VBAT when charger detection not required.
33 E2 FAULT D I VBAT VBUS fault detector input used as EXTERNALVBUSINDICATOR in TUSB1211. The link must enable VBUS fault detection through the USEEXTERNALVBUSINDICATOR register bit, and the polarity must be set through the INDICATORCOMPLEMENT register bit. INDICATORPASSTHRU bit can be used to qualify FAULT with the internal vbusvalid comparator. Connect to GND if not used. This pin is 5-V tolerant.
34 F1 CHRG_POL D I VBAT When connected to GND then CHRG_DET output pin is active low. When connected to VBAT then CHRG_DET output pin is active high.
35 F2 CHRG_DET D O VBAT When CHRG_POL pin is at GND then CHRG_DET is in active low open-drain mode with external RCHRGDET (100K) connected to VBAT. When CHRG_POL pin is at VBAT then CHRG_DET is in active high open-source mode with external RCHRGDET (100K) connected to GND. This pin is 5-V tolerant.
36 D4 PSW D O VBAT Controls an external, active high, VBUS power switch or charge pump. Open source output on VBAT supply when PSW_OSOD bit is 0 (default), open-drain active-low output when PSW_OSOD bit is 1. Requires an external RPSW (100K) pulldown/pullup resistor to GND/VBAT.
(1) Pin = Package Pin coordinate of
(2) A/D: A = Analog pin, D = Digital pin
(3) TYPE: I = Input pin type, O = Output pin type, I/O = Input/Output pin type, POWER = Power supply pin type,
GROUND = Ground type pin
(4) LEVEL = Pin power supply level