SLLS414F March   2000  – August 2015 TUSB2077A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Differential Driver Switching Characteristics (Full-Speed Mode)
    7. 7.7 Differential Driver Switching Characteristics (Low-Speed Mode)
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB Power Management
      2. 8.3.2 Clock Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Vendor ID and Product ID With External Serial EEPROM
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 TUSB2077A Power Supply
    2. 10.2 Downstream Port Power
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Differential Pairs
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PT|48
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PT Package
48-Pin LQFP
Top View
TUSB2077A pt_po_lls414.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BUSPWR 10 I Power source indicator. BUSPWR is an active-low input that indicates whether the downstream ports source their power from the USB cable or a local power supply. For the bus-power mode, this terminal must be pulled low, and for the self-powered mode, this terminal must be pulled to 3.3 V. Input must not change dynamically during operation.
DM0 4 I/O Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.
DM1 13 I/O USB differential data minus. DM1–DM7 paired with DP1–DP7 support up to four downstream USB ports.
DM2 17
DM3 21
DM4 26
DM5 30
DM6 34
DM7 38
DP0 3 I/O Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.
DP1 14 I/O USB differential data plus. DP1–DP7 paired with DM1–DM7 support up to four downstream USB ports.
DP2 18
DP3 22
DP4 27
DP5 31
DP6 35
DP7 39
DP0PUR 2 O Pullup resistor connection. When a system reset happens (RESET being driven to low, but not USB reset) or any logic level change on BUSPWR terminal, DP0PUR output is inactive (floating) until the internal counter reaches a 15-ms time period. After the counter expires, DP0PUR is driven to the VCC (3.3 V) level thereafter until the next system reset event occurs or there is a BUSPWR logic level change.
EECLK 7 O EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK terminal is disabled and must be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3-state serial clock output to the EEPROM with a 100-μA internal pulldown.
EEDATA/
GANGED		 8 I/O EEPROM serial data/power-management mode indicator. When EXTMEM is high, EEDATA/GANGED selects between ganged or per-port power overcurrent detection for the downstream ports. When EXTMEM is low, EEDATA/GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a 100-μA pulldown. This standard TTL input must not change dynamically during operation.
EXTMEM 47 I When EXTMEM is high, the serial EEPROM interface of the device is disabled. When EXTMEM is low, pins 7 and 8 are configured as the clock and data terminals of the serial EEPROM interface, respectively.
GND 5, 24, 43 GND pins must be tied to ground for proper operation.
HUBCFG(1) 40 O Hub configured. Used to control LED indicator. When the hub is configured, HUBCFG is high, which can be used to turn on a green LED. When the hub is not configured, HUBCFG is low, which can be used to turn on a red LED.
MODE 48 I Mode select. When MODE is low, the APLL output clock is selected as the clock source to drive the internal core of the chip and 6-MHz crystal or oscillator can used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other onboard clock source can be used.
OVRCUR1 12 I Overcurrent input. OVRCUR1–OVRCUR7 are active low. For per-port overcurrent detection, one overcurrent input is available for each of the seven downstream ports. In the ganged mode, any OVRCUR input may be used and all OVRCUR pins must be tied together. OVRCUR terminals are active low inputs with noise filtering logic.
OVRCUR2 16
OVRCUR3 20
OVRCUR4 25
OVRCUR5 29
OVRCUR6 33
OVRCUR7 37
PORTPWR(1) 41 O Any port powered. Used to control LED indicator. When any port is powered on, PORTPWR is high, which can be used to turn on a green LED. When all ports are off, PORTPWR is low, which can be used to turn on a red LED.
PORTDIS(1) 42 O No ports disabled. PORTDIS is used for LED indicator control. When no port is disabled, PORTDIS is high, which can be used to turn on a green LED. When any port is disabled, PORTDIS is low, which can be used to turn on a red LED.
PWRON1 11 O Power-on/-off control signals. PWRON1–PWRON7 are active low, push-pull outputs that enables the external power switch device. Push-pull outputs eliminate the pullup resistors which open-drain outputs require. However, the external power switches that connect to these terminals must be able to operate with 3.3-V inputs because these outputs cannot drive 5-V signals.
PWRON2 15
PWRON3 19
PWRON4 23
PWRON5 28
PWRON6 32
PWRON7 36
RESET 6 I RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET is asserted, all logic is initialized. Generally, a reset with a pulse width between 100 μs and 1 ms is recommended after 3.3-V VCC reaches its 90%. Clock signal has to be active during the last 60 μs of the reset window.
SUSPND 1 O Suspend status. SUSPND is an active high output available for external logic power-down operations. During the suspend mode, SUSPND is high. SUSPND is low for normal operation.
VCC 9, 46 3.3-V supply voltage
XTAL1/CLK48 45 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates the 48-MHz and 12-MHz clocks used internally by the ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed.
XTAL2 44 O Crystal 2. XTAL2 is a 6-MHz crystal output. This pin must be left open when using an oscillator.
(1) All LED controls are 3-stated during low-power suspend.