デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
TUSB215-Q1は、USBハイ・スピード(HS)信号コンディショナーで、伝送チャネルでのISI信号損失を補償するよう設計されています。 これにより、USBの電気的コンプライアンスのテストに合格するために役立ちます。
TUSB215-Q1は、特許出願中の設計により、USBロー・スピード(LS)およびフル・スピード(FS)信号でも関係なく動作します。LSおよびFS信号の特性は、TUSB215-Q1により影響を受けず、HS信号は補償されます。
信号のAC昇圧およびDC昇圧をプログラム可能なので、デバイスの性能を微調整してハイ・スピード信号をコネクタで最適化でき、多くの異なるアプリケーションで使用可能です。
さらに、TUSB215-Q1はUSB On-The-Go (OTG)やBattery Charging (BC)プロトコルとも互換性があります。TUSB215-Q1はCDP (Charging Downstream Port)コントローラとしても動作し、下流デバイスとの間で必要なハンドシェークを処理します。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
TUSB215-Q1 | VQFN (14) | 3.50mm×3.50mm |
日付 | 改訂内容 | 注 |
---|---|---|
2017年9月 | * | 初版 |
PIN | I/O | INTERNAL PULLUP/PULLDOWN |
DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
EQ | 1 | I | N/A | USB High Speed AC boost select via external pull down resistor. Sampled upon de-assertion of RSTN. Does not recognize real time adjustments. See application section for details. Auto selects maximum AC boost level when left floating. |
NC | 2, 3 | N/A | N/A | Leave unconnected. |
DC_BOOST(2)/ENA_HS | 4 | I/O | In I2C mode: Reserved for TI test purpose. In non-I2C mode: At reset: 3-level input signal DC_BOOST. USB High Speed DC signal boost selection. H (pin is pulled high) – 80 mV M (pin is left floating) – 60 mV L (pin is pulled low) – 40 mV After reset: Output signal ENA_HS. Flag indicating that channel is in High Speed mode. Asserted upon: 1. Detection of USB-IF High Speed test fixture from an unconnected state followed by transmission of USB TEST_PACKET pattern. 2. Squelch detection following USB reset with a successful HS handshake [HS handshake is declared to be successful after single chirp J chirp K pair where each chirp is within 18 μs – 128 μs]. |
|
D2P | 5 | I/O | N/A | USB High Speed positive port. |
D2M | 6 | I/O | N/A | USB High Speed negative port. |
GND | 7 | PWR | N/A | Ground |
VREG | 8 | O | N/A | 1.8-V LDO output. Only enabled when operating in High Speed mode. Requires 0.1-µF external capacitor to GND to stabilize the core. |
D1M | 9 | I/O | N/A | USB High Speed negative port.. |
D1P | 10 | I/O | N/A | USB High Speed positive port. |
SDA(1) | 11 | I/O | RSTN asserted: 500 kΩ PD | I2C Mode: Bidirectional I2C data pin [I2C address = 0x2C]. In non I2C mode: Reserved for TI test purpose. |
VCC | 12 | PWR | N/A | Supply power |
SCL(1)/CD | 13 | I/O | RSTN asserted: 500 kΩ PD | In I2C mode: I2C clock pin [I2C address = 0x2C]. Non I2C mode: After reset: Output CD. Flag indicating that a USB device is attached (connection detected). Asserted from an unconnected state upon detection of DP or DM pull-up resistor. De-asserted upon detection of disconnect. |
RSTN | 14 | I | 500 kΩ PU | Device disable/enable. Low – Device is at reset and in shutdown, and High – Normal operation. Recommend 0.1-µF external capacitor to GND to ensure clean power on reset if not driven. If the pin is driven, it must be held low until the supply voltage for the device reaches within specifications. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage Range | VCC | -0.3 | 6 | V |
Voltage Range on I/O pins | DxP, DxM, RSTN, EQ, SCL, SDA, DC_BOOST, VREG | -0.3 | 3.8 | V |
Tstg | Storage temperature | -65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage | 4.4 | 5 | 5.5 | V | |
TA | Ambient temperature | TUSB215Q1 | -40 | 105 | °C | |
TJ | Junction temperature | TUSB215Q1 | -40 | 125 | °C |
THERMAL METRIC(1) | UNIT | ||
---|---|---|---|
RGY (VQFN) | |||
14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 49.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 52.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 24.2 | °C/W |
ΨJT | Junction-to-top characterization parameter | 2.2 | °C/W |
ΨJB | Junction-to-board characterization parameter | 24.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER | ||||||
IACTIVE_HS | High-speed active curent | USB channel = HS mode; 480 Mbps traffic; VCC = 5V; VCC supply stable; DC Boost = 60 mV | 18 | 30 | mA | |
IIDLE_HS | High-speed idle current | USB channel = HS mode; no traffic; VCC = 5V; VCC supply stable; DC Boost = 60 mV | 13 | 22 | mA | |
ISUSPEND_HS | High-speed suspend current | USB channel = HS suspend mode; VCC = 5V; VCC supply stable | 0.76 | 1.5 | mA | |
IFS_LS | Full/Low speed current | USB channel = FS mode or LS mode; VCC = 5V | 0.77 | 1.5 | mA | |
IDISCONNECT | Disconnect current | Host side application; No device attachment; VCC = 5V | 0.86 | 1.5 | mA | |
IRSTN | Disable current | RSTN driven low; VCC supply stable; VCC = 5V | 22 | 80 | µA | |
ILKG_FS | Pin fail-safe leakage current for SDA, SCL, DC_BOOST, DxP/N, RSTN | VCC = 0 V; Pin at 3.6 V | 40 | µA | ||
RSTN | ||||||
VIH | High-level input voltage | VCC = 4.4V | 2 | 3.6 | V | |
VIL | Low-level input voltage | VCC = 5.5V | 0 | 0.8 | V | |
IIH | High-level input current | VIH = 3.6 V | -4 | 4 | µA | |
IIL | Low-level input current | VIL = 0 V | -11 | 11 | µA | |
EQ | ||||||
REQ | External pull-down resistor on EQ pin. | AC Boost Level 0 | 160 | Ω | ||
AC Boost Level 1 | 1.4 | 2 | kΩ | |||
AC Boost Level 2 | 3.7 | 3.9 | kΩ | |||
AC Boost Level 3 | 6 | kΩ | ||||
CD, ENA_HS | ||||||
VOH | High-level output voltage | IO = -50µA | 2.4 | V | ||
VOL | Low-level output voltage | IO = 50µA | 0.4 | V | ||
SCL, SDA | ||||||
CI2CBUS | I2C Bus capacitance | 4 | 150 | pF | ||
VIH | SDA and SCL input high level voltage | VCC = 4.4V | 2 | 3.6 | V | |
VIL | SDA and SCL input Low level voltage | VCC = 5.5V | 0.8 | V | ||
VSDA_OL | SDA low-level output voltage | 4.7kΩ pullup to 3.6V; VCC = 4.4V | 0.4 | V | ||
ISDA_OL | SDA Low level output current | VCC = 5.5V; I2C pulled up to 3.6V | 1.1 | mA | ||
DC_BOOST | ||||||
VIH | High-level input voltage | VCC = 5V | 2.4 | 3.6 | V | |
VIM | Mid-level input voltage | VCC = 5V | 1.6 | V | ||
VIL | Low-level input voltage | VCC = 5V | 0 | 0.4 | V | |
DxP, DxM | ||||||
CIO_DXX | Capacitance to GND | Measured with LCR meter and device powered down. 1 MHz sinusoid, 30 mVpp ripple | 2.7 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
FBR_DXX | DxP/M Bit Rate | USB channel = HS mode; 480 Mbps traffic; VCC supply stable | 480.24 | Mbps | ||
tRISE_DXX | DxP/M rise time | 10% - 90%; VCC = 5.5V; Max AC Gain; | 100 | ps | ||
tFALL_DXX | DxP/M fall time | 90% - 10%; VCC = 5.5V; Max AC Gain; | 100 | ps | ||
tRSTN_PULSE_WIDTH | Minimum width to detect a valid RSTN signal assert when the pin is actively driven | VCC = 4.4 V; Refer to Figure 1 | 20 | µs | ||
tSTABLE | VCC stable before RSTN de-assertion | Refer to Figure 1 | 100 | µs | ||
tVCC_RAMP | VCC ramp time | 0.2 | 100 | ms |
The TUSB215-Q1 is a USB High-Speed (HS) signal conditioner, designed to compensate for ISI signal loss in a transmission channel. TUSB215-Q1 has a patent-pending design which is agnostic to USB Low Speed (LS) and Full Speed (FS) signals and does not alter their signal characteristics, while HS signals are compensated. In addition, the design is compatible with USB On-The-Go (OTG) and Battery Charging (BC) specifications. The TUSB215-Q1 provides USB Charging Downstream Port (CDP) controller for applications in which USB host or hub do not have this function.
Programmable signal AC boost through an external resistor on EQ pin permits fine tuning device performance to optimize signals helping to pass USB HS electrical compliance tests at the connector. Additional DC Boost configurable by three level input DC_BOOST pin helps overcoming the cable losses.
The EQ pin of the TUSB215-Q1 is used to configure the AC boost of the device. The four levels of AC boost are set through different values of an external pulldown resistor at this pin.
The DC_BOOST pin of the TUSB215-Q1 is a tri-level pin, used to set the DC gain of the device according to Table 1.
DC BOOST SETTING VIA PIN STRAP | |
---|---|
DC_BOOST | DC Boost Setting (mV) |
VIL | 40 |
VIM | 60 |
VIH | 80 |
The TUSB215-Q1 main function is a signal conditioner offering the EQ/Boost features to the incoming DP/DM signals. For applications in which USB host or hub do not provide USB BC charging downstream port (CDP) functionality, the TUSB215-Q1 can perform this task.
TUSB215-Q1 automatically detects a LS connection and does not enable signal compensation. CD pin is asserted high.
TUSB215-Q1 automatically detects a FS connection and does not enable signal compensation. CD pin is asserted high.
TUSB215-Q1 automatically detects a HS connection and will enable signal compensation as determined by the configuration of the DC_BOOST pin and the external pulldown resistance on its EQ pin. CD pin asserted high.
TUSB215-Q1 is disabled when its RSTN pin is asserted low. In shutdown mode, the USB channel is still fully operational but there is neither signal compensation nor any indication from the CD pin as to the status of the channel.
TUSB215-Q1 support 100 kHz I2C for device configuration, status readback and test purposes. This controller is enabled after SCL and SDA pins are sampled high shortly after de-assertion of RSTN. In this mode, the register as described in Table 2 can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is necessary to set CFG_ACTIVE bit and reset it to zero after making changes to the EQ and DC Boost level registers to restart the state machine.
NOTE
All registers or fields in Table 2 which are not specifically mentioned are considered reserved. The default value of these reserved registers or fields must not be changed. It is suggested to perform a read-modify-write operation to maintain the default value of the reserved fields.
Offset | Bit(s) | Name | Type | Default | Description |
---|---|---|---|---|---|
0x01 | 6:4 | ACB_LVL | RW | XXX (Sampled from EQ pin at reset) |
Sets the level of AC boost 000 :Level 0 AC boost programmed [MIN] 001 : Level 1 AC boost programmed 011 : Level 2 AC boost programmed 111 : Level 3 AC boost programmed [MAX] |
0x03 | 0 | CFG_ACTIVE | RW | 1b |
Configuration mode 0 : Normal mode. State machine enabled. 1 : Configuration mode: State machine disabled. After reset, if I2C mode is true (SCL and SDA are both pulled high) it is maintained until it is cleared by an I2C write, but, if I2C mode is not true, it is cleared automatically. |
0x0E | 2:0 | DCB_LVL | RW | XXX (Sampled from DC_BOOST pin at reset) |
Sets the level of DC Boost 011 : 40mV (DC_Boost = L) 101 : 60mV (DC_Boost = M, default) 111 : 80mV (DC_Boost = H) |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The primary purpose of the TUSB215-Q1 is to re-store the signal integrity of a USB High Speed channel up to the USB connector. The loss in signal quality stems from reduced channel bandwidth due to high loss PCB trace and other components that contribute a capacitive load. This can cause the channel to fail the USB near end eye mask. Proper use of the TUSB215-Q1 can help to pass this eye mask. Additionally the DC Boost helps overcoming DC losses from cables and traces.
A secondary purpose is to use the CD pin of the TUSB215-Q1 to control other blocks on the customer platform if so desired. The TUSB215-Q1 also provides CDP controller function.
A typical application is shown in Figure 6. In this setup, D2P and D2M face the USB connector while D1P and D1M face the USB host or hub. If desired, the orientation may be reversed [that is, D2 faces transceiver and D1 faces connector].
For this design example, use the parameters shown in the table below.
PARAMETER | VALUE | |||
---|---|---|---|---|
VCC (4.4 V to 5.5 V) | 5 V | |||
I2C support required in system (Yes/No) | No | |||
AC Boost | REQ | Level | AC Boost Level 2: REQ = 3.83 k |
|
0-Ω | 0 | |||
1.69 k ±1% | 1 | |||
3.83 k ± 1% | 2 | |||
DNI | 3 | |||
DC Boost | RDC1 | RDC2 | Level | Mid DC Level: RDC1 = DNI RDC2 = DNI |
22 kΩ - 47 kΩ | Do Not Install (DNI) | 40 mV Low DC boost | ||
DNI | DNI | 60 mV Mid DC boost | ||
47 kΩ | 24 kΩ | 80 mV High DC boost |
TUSB215-Q1 requires a valid reset signal as described in the power supply recommendations section. The capacitor at RSTN pin is not required if a microcontroller drives the RSTN pin according to recommendations.
VREG pin is the internal LDO output that requires a 0.1-μF external capacitor to GND to stabilize the core.
The ideal AC boost setting is dependent upon the signal chain loss characteristics of the target platform. The general recommendation is to start with AC boost level 0, and then increment to AC boost level 1, etc. if permissible. Same applies to the DC Boost setting where it is recommended to plan for the required pads or connections to change boost settings, but to start with DC boost level 1.
In order for the TUSB215-Q1 to recognize any change to the AC and DC Boost settings, the RSTN pin must be toggled. This is because the configuration is latched on power up and the inputs are ignored thereafter.
NOTE
The TUSB215-Q1 compensates for DC attenuation in the signal path according to the configuration of the DC_BOOST pin. This pin is not 5V tolerant and therefore when selecting the highest DC boost level, the voltage level at DC_BOOST pin must be less than 3.6V.
Placement of the device is also dependent on the application goal. Table 4 summarizes our recommendations.
PLATFORM GOAL | SUGGESTED DEVICE PLACEMENT |
---|---|
Pass USB Near End Mask | Close to measurement point |
Pass USB Far End Eye Mask | Close to USB PHY |
Cascade multiple devices to improve device enumeration | Midway between each USB interconnect |
NOTE
USB-IF certification tests for High Speed eye masks require the mandated use of the USB-IF developed test fixtures. These test fixtures do not require the use of oscilloscope probes. Instead they use SMA cables. More information can be found at the USB-IF Compliance Updates Page. It is located under the ‘Electricals’ section, ID 86 dated March 2013.
The following procedure must be followed before using any oscilloscope compliance software to construct a USB High Speed Eye Mask:
On power up, the interaction of the RSTN pin and power on ramp could result in digital circuits not being set correctly. The device should not be enabled until the power on ramp has settled to 4.4 V or higher to ensure a correct power on reset of the digital circuitry. If RSTN cannot be held low by microcontroller or other circuitry until the power on ramp has settled, then an external capacitor from the RSTN pin to GND is required to hold the device in the low power reset state.
The RC time constant should be larger than five times of the power on ramp time (0 to VCC). With a typical internal pullup resistance of 500 kΩ, the recommended minimum external capacitance is calculated as: